LSI Logic Confidential
13-14
SDRAM Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
microseconds prior to writing the External DRAM Configuration register
(
) so the DRAM clocks are stable for the required period (per
DRAM data sheet specs) prior to initialization of the DRAMs. This
register should only be written once after the DMN-8600 is reset (via the
Chip Reset bit in the Host Control register).
The DRAM Clock Control register is a memory mapped register at offset
0x30010 from the DMN-8600 address window, shown below
SDRAM Clock Control Register
Cbus Address: 0x30010
DQSinTapSel
[23:16]
DQSinTapSel specifies the delay from the DQS input
strobe to input capture. The delay is in units of 1/256 of
the internal clock period.
InClkTapSel
[15:8]
For SDR DRAM, InClkTapSel specifies the delay from the
internal (DoMiNoClock) clock to the input capture. For
DDR dram, this field specifies the delay from write data
out to DQS out. The delay is in units of 1/256 of the
internal clock period.
OutClkTapSel
[7:0]
OutClkTapSel specifies the delay from the internal
(DMN-8600 Clock) clock to the DRAM_CLK output clock.
The delay is in units of 1/256 of the internal clock period.
13.8 SDRAM Arbitration and Throttle Registers
DRAM requests are arbitrated by priority according to the latency
requirements of the requestor. The nominal request priority of each
31
24
23
16
Reserved
DQSinTapSel
15
8
7
0
InClkTapSel
OutClkTapSel
Содержание DMN-8600
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