LSI Logic Confidential
15-26
Serial I/O Port
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Bits [8:1] of the SIO Top Level Module Interrupt Status register are ORed
together with bits [11:1] of the SIO Top Level DMA Interrupt Status
register to create a single interrupt signal, which is sent to the SPARC
processor. The SPARC processor must read both of these Interrupt
Status registers to determine which module/DMA channel is the source
of the interrupt, and act accordingly.
Note:
Each of the following Interrupt Status bits signals whether
the corresponding SIO module (the module indicated in the
bit’s name) has an interrupt waiting to be serviced.
1 = Waiting
0 = Done
Note:
Before clearing an Interrupt Status bit, software must
resolve the corresponding module’s interrupt, as described
in the particular module’s section in this chapter. Note that
the procedure to resolve the interrupt varies from module
to module. Refer to
Section 15.5.1, “Interrupt Hierarchy,”
for more details.
IR2T
IR2 Transmit Interrupt Status
8
IR1R
IR1 Receive Interrupt Status
7
IR1T
IR1 Transmit Interrupt Status
6
UA2I
UART2 Interrupt Status
5
UA1I
UART1 Interrupt Status
4
IDCI
IDC Interrupt Status
3
SPIC
SPI Cycle Done Interrupt Status
2
ACT
Action Bit
0
This bit is an action bit. The value of this bit is written to
any selected bits during register writes. Bits to be written
are selected by placing a 1 in each desired location as
the register is written. Any bit positions that contain a 0
during register writes remain unchanged.
This bit always reads back as 0.
Содержание DMN-8600
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