LSI Logic Confidential
13-10
SDRAM Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
rising edge of clock. Refresh cycles (one to each bank) are generated at
the rate programmed by the refresh interval field of the DRAM control
register.
13.6 External SDRAM Configuration Register
The 32-bit Configuration Register that resides in the SDRAM is shown
below. The first time the external configuration is written after reset, a
DRAM initialization sequence is performed. The fields within the
Configuration Register are described below.
External DRAM Configuration Register
Cbus Address: 0x30014
SD/DDR
31
SDRAM/DDR. Indicates the type of external DRAM. Not
applicable to the embedded part.
0 = Single Data Rate SG/SDRAM
1 = DDR SG/SDRAM
Page Size
[30:29]
PAGE size. All pages are 32-wide. For 16-bit wide parts,
refers to the page size of a pair of parts. The tile height
is determined by this field.
00 = Page size is 32x128. Tile height is 8, this requires
a bank count (bit 22) of 8
01 = Page size is 32x256. Tile height is 16.
10 = Page size is 32x512. Tile height is 32.
DRAM Size
[28:27]
DRAM size. For 16 bit wide parts, refers to the size of a
pair of parts.
31
30
29
28
27
26
24
23
22
21
20
19
18
17
16
SD/DDR
Page Size
DRAM Size
Part Count
SG/S
D R
Bank
C
Drive
Stren
Last Data
to Read
LtoF L
LastDin2P
Latency
15
14
13
12
11
10
9
8
7
6
5
0
WrC2D
ActiveP Latency
Prech
Latency
Act L RAS Latency CAS L
Refresh Interval
Содержание DMN-8600
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