
194
c
HAPTER
8:
Service
Model 372 AC Resistance Bridge and Temperature Controller
OVL) is displayed. The overload can occur at either “VCMPOS” or “VCNEG” points in
the instrumentation amplifier circuit. Refer to FIGURE 8-3 for the location of “VCM-
POS” and “VCNEG” monitoring points. The signal voltage at either monitoring point
can be viewed on an oscilloscope by using the monitor output described in section
4.5.3.
Usual causes for this error include:
D
Improperly shielded measurement leads.
D
An improperly grounded Dewar case.
To resolve this condition, first verify that the experimental Dewar case is properly
connected to the instrument measurement common and earth ground (section
3.5.5). Next, verify the integrity of the measurement lead shields. Use of the Common
Mode Reduction (CMR) feature of the Model 372 reduces this effect electronically. It
is particularly effective at excitation currents above 1 µA.
8.12.1.3 VDIF OVL (Differential Overload — Measurement Input Only)
The input stage of the voltage measurement side of the measurement input is a very
high input impedance instrumentation amplifier with a high gain of 1000 (10 at volt-
age excitations of 20 mV and above). If the combination of signal and differential
noise components cause the output of this stage to exceed 10 V peak, the differential
overload error (VDIF OVL) is displayed. The overload occurs at the “VDIF” point in the
instrumentation amplifier circuit. Refer to FIGURE 8-3 for the location of the “VDIF”
monitoring point. The signal voltage can be viewed on an oscilloscope by using the
monitor output described in section 4.5.3.
Usual causes of this error include:
D
An attempt to measure a resistance that is much greater (2 orders of magnitude)
than the selected range.
D
An open connection of one or both of the voltage measurement leads.
D
Significant differential noise on current and/or voltage leads.
To resolve this condition, first verify that a reasonable resistance range has been
selected for the measurement. Next, verify the integrity of the voltage lead connec-
tions to the measured resistance. If the error persists, verify that the voltage pair of
leads is twisted and shielded. Likewise, the current pair of leads should be twisted and
shielded. Twisted pair wiring reduces the differential signals potentially created by
environmental noise. However, there is no advantage gained by twisting the current
pair of leads together with the voltage pair of leads. When twisted leads are not an
option (inside a Dewar), the shielding must be verified adequate for the task. The
Dewar itself can act as a shield when the case is properly connected. Ensure that the
experimental Dewar case is properly connected to the measurement common of the
instrument and earth ground. Refer to Installation section 3.5.5.
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