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6.2.6 Status System Detail: Status Byte Register and Service Request 127
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6.2.6 Status System
Detail: Status Byte
Register and Service
Request As shown in FIGURE 6-1, the status byte register receives the summary bits from the
standard event status register. The status byte is used to generate a service request
(SRQ). The selection of summary bits that generates an SRQ is controlled by the ser-
vice request enable register.
6.2.6.1 Status Byte Register
The summary messages from the standard event status register set or clear the sum-
mary bits of the status byte register (FIGURE 6-3). These summary bits are not
latched. Clearing the standard event status register will clear the corresponding sum-
mary bit in the status byte register. The bits of the status byte register are described as
follows:
D
Ramp Done—Sample Heater (RAMPS) Bit (7): this bit is set when thesample
heater setpoint ramp is completed.
D
Request Service (RQS)/Master Summary Status (MSS), Bit (6): this bit is set when a
summary bit and the summary bit’s corresponding enable bit in the service
request enable register are set. Once set, the user may read and clear the bit in
two different ways, which is why it is referred to as both the RQS and the MSS bit.
When this bit goes from low to high, the service request hardware line on the bus
is set; this is the RQS function of the bit (section 6.2.6.3). In addition, the status of
the bit may be read with the *STB? query, which returns the binary weighted sum
of all bits in the status byte; this is the MSS function of the bit.
Performing a serial poll will automatically clear the RQS function, but it will not clear
the MSS function. A *STB? will read the status of the MSS bit (along with all of the
summary bits), but also will not clear it. To clear the MSS bit, either clear the event
register that set the summary bit or disable the summary bit in the
service request enable register.
D
Event Summary (ESB), Bit (5): this bit is set when an enabled standard event has
occurred.
D
Sensor Overload (OVLD), Bit (4): this bit is set when there is a sensor overload con-
dition on either input. The following errors can trigger this bit to be set: CS OVL,
VCM OVL, VDIF OVL, VMIX OVL, R. OVER, R. UNDER, T. OVER, T. UNDER.
D
Alarming (ALARM), Bit (3): this bit is set when an input is in an alarming state, and
the Alarm Visible parameter is on.
D
Valid Reading— measurement input (VRM), Bit (2): this bit is set when the hard-
ware and firmware filters are settled and a valid active measurement channel
input reading can be taken.
D
Valid Reading—Control Input (VRC), Bit (1): this bit is set when the hardware and
FIGURE 6-2 Standard event status register
7 6 5 4 3 2 1 0
PON CME EXE QYE OPC
AND
OR
AND
AND
AND
AND
7 6 5 4 3 2 1 0
8 4 2 1
Standard event
Status register
*ESR?
( *ESR? reads and
clears the register)
Standard event
Status enable register
*ESE, *ESE?
Not
used
Not
used
Not
used
PON CME EXE QYE OPC
Not
used
Not
used
Not
used
– Decimal
– Name
– Bit
– Bit
– Decimal
– Name
To event summary
bit (ESB) of status
byte register
(see FIGURE 6-1)
16 32 64 128
8 4 2 1 16 32 64 128