Section 7: TSP command reference
Series 2600B System SourceMeter® Instrument Reference Manual
7-306
2600BS-901-01 Rev. C / August 2016
status.operation.instrument.smuX.*
This attribute contains the operation status SMU X summary register set.
Type
TSP-Link accessible
Affected by
Where saved
Default value
Attribute
- -
- -
- -
- -
.condition (R)
Yes
Not applicable
Not saved
Not applicable
.enable (RW)
Yes
Status reset
Not saved
0
.event (R)
Yes
Status reset
Not saved
0
.ntr (RW)
Yes
Status reset
Not saved
0
.ptr (RW)
Yes
Status reset
Not saved
1049 (All bits set)
Usage
operationRegister
= status.operation.instrument.smu
X
.condition
operationRegister
= status.operation.instrument.smu
X
.enable
operationRegister
= status.operation.instrument.smu
X
.event
operationRegister
= status.operation.instrument.smu
X
.ntr
operationRegister
= status.operation.instrument.smu
X
.ptr
status.operation.instrument.smu
X
.enable =
operationRegister
status.operation.instrument.smu
X
.ntr =
operationRegister
status.operation.instrument.smu
X
.ptr =
operationRegister
operationRegister
The status of the operation status SMU X summary register; a zero (0) indicates no
bits set (also send 0 to clear all bits); other values indicate various bit settings
X
Source-measure unit (SMU) channel (for example
status.operation.instrument.smua.enable
applies to SMU channel A)
Details
These attributes are used to read or write to the operation status SMU X summary registers. Reading
a status register returns a value. The binary equivalent of the returned value indicates which register
bits are set. The least significant bit of the binary number is bit B0, and the most significant bit is bit
B15. The binary equivalent of the value indicates which register bits are set. In the binary equivalent,
the least significant bit is bit B0, and the most significant bit is bit B15. For example, if a value of
1.02
(which is 1,025) is read as the value of the condition register, the binary equivalent is
0000 0100 0000 0010. This value indicates that bit B0 and bit B10 are set.
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
**
>
>
>
>
>
>
>
>
>
>
>
>
>
>
*
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
* Least significant bit
** Most significant bit
For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to
Enable and transition registers
(on page E-19). The individual bits of this
register are defined in the following table.