TH-A9
1-26
MC44724AVFU (IC554) : VIDEO ENCODER
1
16
48
33
17 ~ 32
64 ~ 49
~
~
Y/G1Vdd
CVBS/Cb/B1Vdd
C/Cr/R1Vdd
Y/G1
Y/G1
CVBS/Cb/B1
CVBS/Cb/B1
C/Cr/R1
C/Cr/R1
Vref1
iBIAS1
ChipA
DVdd
DVdd
DVss
DVss
EXT
+
H.V
12C / SPI
SO
Clock
Reset
PAL/NTSC
Y
DEMAX
cb
cr
SD
A/SI
SCL/SCK
SEL
TEST
DL
Vss
DL
Vdd
TEST
Y/G2
Y/G2
CVBS/Cb/B2
CVBS/Cb/B2
C/Cr/R2
C/Cr/R2
Vref2
Ibias
DAVdd
DAVss
BIAS
DA
C
DA
C
D
A
C
BIAS
D
A
C
D
A
C
D
A
C
Output Selector
0
0
0
0
0
0
RGB
matrix
+
CGMS,
wss gen
CCwss gen
Sync_ generator
0
0
0
off_set
Modulator
sub carrier
gen
Copy,
protection
bus
F/Vsync
Hsync
Y/G2Vdd
CVBS/Cb/B2Vdd
C/Cr/R2Vdd
DVIN[7:0]
TP[8:1]
TVIN
TP[0]IN
1.Terminal layout
2.Block diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CVBS/Cb/B1
CVBS/Cb/B1
CVBS/Cb/B1Vdd
Y/G1
Y/G1
Y/G1/Vdd
C/Cr/R1
C/Cr/R1
C/Cr/R1Vdd
DAVss
TBIAS1
Vref1
DAVdd
Vref2
TBIAS2
NC
CVBS/Cb/B2
CVBS/Cb/B2
CVBS/Cb/B2Vdd
Y/G2
Y/G2
Y/GVdd
C/Cr/R2
C/Cr/R2
C/Cr/R2Vdd
ChipA
TEST
DVdd
CLOCK
DVss
Reset
PAL/NTSC
O
O
-
O
O
-
O
O
-
-
O
-
-
-
O
-
O
O
-
O
O
-
O
O
-
-
I
-
I
-
I
I
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SO
SDA/SI
SCL/SCK
SEL
DVdd
DVss
DVIN7
DVIN6
DVIN5
DVIN4
DVIN3
DVIN2
DVIN1
DVIN0
TVIN
EXT
F/Vsyac
Chsyac
DATST
TP-8
TP7
TP6
TP5
DVss
DVdd
TP4
TP3
TP2
TP1
TP0
DLVdd
DLVss
-
I
I
I
--
--
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
Analog composite drive signal (+)
Analog composite drive signal (-)
Power supply for CVBS/Cb/B DAC1
Analog brightness signal/G drive signal (+)
Analog brightness signal/G drive signal (-)
Power supply for Y/G DAC
Analog chroma signal (+)
Analog chroma signal (-)
Power supply for C/Cr/RDAC
Connect to ground for DAC
Standard BIAS for DAC1
Standard voltage for DAC1
Power supply for DAC
Standard voltage for DAC2
Standard BIAS for DAC2
Non connect
Analog composite drive signal (+)
Analog composite drive signal (-)
Power supply for CVBS/Cb/B DAC2
Analog brightness signal/G drive signal (+)
Analog brightness signal/G drive signal (-)
Power supply for Y/G DAC
Analog chroma signal (+)
Analog chroma signal (-)
Power supply for C/Cr/RDAC2
Chip address selection
Connect to test pin
Digital ground
Clock signal input (27MHz)
Power supply for digital circuit
Reset signal input L:ON
Selection NTSC/PAL NTSC:L PAL:H
Non connect
SPI Mode : Serial data input
Serial clock input
Power supply for serial data,chip select,digital
Power supply for digital circuit
Digital ground
Y data input / test data I/O
Y data input / test data I/O
Y data input / test data I/O
Y data input / test data I/O
Y data input / test data I/O
Y data input / test data I/O
Y data input / test data I/O
Y data input / test data I/O
VIDEO mute on Reset(0:nomal, 1:mute)
Frame output / VBI information input
Frame / Vertical, synchronous I/O
The horizontal, synchronous I/O
Data input
Multiplex data input
Multiplex data input
Multiplex data input
Multiplex data input
Ground for digital circuit
Power supply for digital circuit
Data input / Test data I/O
Data input / Test data I/O
Data input / Test data I/O
Data input / Test data I/O
Data input / Test data I/O
Power supply for D/A converter
Ground for D/A converter
3.Pin function
No.
Symbol
Function
No.
Symbol
Function
