TH-A9
1-24
Clock
Generator
Row
address
buffer &
Refresh
counter
Bank B
Bank A
Ro
w decoder
Sense amplifier
Column decoder
& latch circuit
DQM
Command decoder
Control logic
Column
address
buffer &
burst
counter
Data counter
Latch circuit
Input & output
b
uff
er
DQ
Mode
register
CLK
CKE
CS
RAS
CAS
WE
Address
1
2,3
4
5,6
7
8,9
10
11,12
13
14
15
16
17
18
19,20
21~24
25
26
27~32
33
34
35
36
37
38
39,40
41
42,43
44
45,46
47
48,49
50
VCC
DQ0,1
VSS
DQ2,3
VDD
DQ4,5
VSS
DQ6,7
VCC
LDQM
WE
CAS
RAS
CS
A11,10
A0~3
VCC
VSS
A4~9
NC
CKE
CLK
UDQM
NC
VCC
DQ8,9
VSS
DQ10,11
VDD
DQ12,13
VSS
DQ14,15
VSS
Power supply
Data input/output
Connect to GND
Data input/output
Power supply
Data input/output
Connect to GND
Data input/output
Power supply
Lower DQ mask enable
Write enable
Column address strobe
Row address strobe
Chip enable
Address inputs
Address inputs
Power supply
Connect to GND
Address inputs
Non connect
Clock enable
System clock input
Upper DQ mask enable
Non connect
Power supply
Data input/output
Connect to GND
Data input/output
Power supply
Data input/output
Connect to GND
Data input/output
Connect to GND
Pin No.
Symbol
Description
Pin No.
Symbol
Description
2.Pin function
HY57V161610DTC8 or KM416S1120DT-G8 (IC504,IC505) : 16MB SDRAM
1.Block diagram