TH-A9
1-27
MN102L25GHW(IC401) : UNIT CPU
1. Pin layout
ADSCIRQ
ODCIRQ
DECIRQ
WAKEUP
ODCIRQ2
ADSEP
RST
VDD
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8
VSS
D0
D1
D2
D3
TRVSW
HMFON
CD/DVD
/ADPD
HAGUP
TXSEL
A20
VSS
A19
A18
A17
A16
A15
A14
A13
A12
VDD
A11
A10
A9
A8
D4
D5
D6
D7
A7
A6
A5
A4
NMI
-
-
SDOUT
SDIN
CPSCK
U2SDT
S2UDT
SCLKO
VDD
EPDO
DPDI
EPSK
EPCS
VSS
HSSEEK
CIRCEN
REQ
BUSY
SLEEP
FEPEN
WAIT
RE
SPMUTE
WEN
CS0
CS1
CS2
CS3
DRVMUTE
SPKICK
LSIRST
WORD
A0
A1
A2
A3
VDD
SYSCLK
VSS
XI
XO
VDD
ADSCEN
TRS
FGIN
VDD
OSCI
OSCO
MODE
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MN102L25GHW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
O
-
-
-
-
I
O
I
O
O
O
O
O
O
O
O
-
O
O
O
O
O
O
O
O
-
O
O
O
O
I
WAIT
RE
SPMUTE
WEN
CS0
CS1
CS2
CS3
DRVMUTE
SPKICK
LSIRST
WORD
A0
A1
A2
A3
VDD
SYSCLK
VSS
XI
XO
VDD
OSCI
OSCO
MODE
A4
A5
A6
A7
A8
A9
A10
A11
VDD
A12
A13
A14
A15
A16
A17
A18
A19
VSS
A20
TXSEL
HAGUP
/ADPD
CD/DVD
HMFON
TRVSW
2.Pin function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
FGIN
TRS
ADSCEN
VDD
FEPEN
SLEEP
BUSY
REQ
CIRCEN
HSSEEK
VSS
EPCS
EPSK
DPDI
EPDO
VDD
SCLKO
S2UDT
U2SDT
CPSCK
SDIN
SDOUT
-
-
NMI
ADSCIRQ
ODCIRQ
DECIRQ
WAKEUP
ODCIRQ2
ADSEP
RST
VDD
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8
VSS
D0
D1
D2
D3
D4
D5
D6
D7
I
O
-
O
O
I
O
O
O
-
O
O
I
O
-
I
I
O
O
I
O
-
-
-
I
I
I
O
I
I
I
-
I
I
I
I
I
I
I
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin No.
Pin No.
Symbol
Symbol
I/O
I/O
Function
Function
Micon wait signal input
Read enable
Write enable
Non connect
Chip select for ODC
Chip select for ZIVA
Chip select for outer ROM
Driver mute
Non connect (Spin kick output)
LSI reset
Bus selection input
Address bus 0 for CPU
Address bus 1 for CPU
Address bus 2 for CPU
Address bus 3 for CPU
Power supply
System clock signal output
GND
Non connect (Connect to VSS)
Non connect
Power supply
Clock signal input (13.5MHz)
Clock signal output (13.5MHz)
CPU Mode selection input
Address bus 4 for CPU
Address bus 5 for CPU
Address bus 6 for CPU
Address bus 7 for CPU
Address bus 8 for CPU
Address bus 9 for CPU
Address bus 10 for CPU
Address bus 11 for CPU
Power supply
Address bus 12 for CPU
Address bus 13 for CPU
Address bus 14 for CPU
Address bus 15 for CPU
Address bus 16 for CPU
Address bus 17 for CPU
Address bus 18 for CPU
Address bus 19 for CPU
GND
Address bus 20 for CPU
TX select
Detection switch of traverse inside
Photo input
Serial enable signal for ADSC
Power supply
Serial enable signal for FEP
Standby signal for FEP
Communication busy
Communication request
CIRC command select
Seek select
GND
Chip select signal for EEPROM
Clock signal for EEPROM
Input data for EEPROM
Output data for EEPROM
Power supply
Communication clock
Communication input data
Communication output data
Clock for ADSC serial
ADSC serial data input
ADSC serial data output
Non connect
Non connect
Non connect
Interrupt input of ADSC
Interrupt input of ODC
Interrupt input of ZIVA
Non connect
Address data selection input
Reset input
Power supply
Test signal 1 input
Test signal 2 input
Test signal 3 input
Test signal 4 input
Test signal 5 input
Test signal 6 input
Test signal 7 input
Test signal 8 input
GND
Data bus 0 of CPU
Data bus 1 of CPU
Data bus 2 of CPU
Data bus 3 of CPU
Data bus 4 of CPU
Data bus 5 of CPU
Data bus 6 of CPU
Data bus 7 of CPU
