TH-A9
1-39
ZIVA3-PEO (4/5)
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
3.3 V supply voltage for I/O signals.
Video data bus for byte-serial CbYCrY data.
In power up, the decoder does not drive VDATA. In boot-up, the decoder uses the operation
configuration parameters or tri-state VDATA.
Core logic and I/O signal grounding.
Video data bus for byte-serial CbYCrY data.
In power up, the decoder does not drive VDATA. In boot-up, the decoder uses the operation
configuration parameters or tri-state VDATA.
Programmable I/O pin, which enters input mode after resetting.
Video data bus for byte-serial CbYCrY data.
In power up, the decoder does not drive VDATA.
In boot-up, the decoder uses the operation configuration parameters or tri-state VDATA.
Programmable I/O pin, which enters input mode after resetting.
Horizontal sync. After the negative-going edge of VSYNC, the decoder starts pixel data
output for the new horizontal line.
Vertical sync, which is bi-directional. After the negative-going edge of VSYNC, the decoder
outputs the highest border of the new field for the first SYNC. VSYNC can receive either V
sync or upper/lower field notification from an external source.
ICE-1937 bitstream output or IEO-958 format PCM data output.
3.3 V supply voltage for I/O signals.
PCM data output in 8 channels. Serial audio sample relative to the DA-BCK clock.
Core logic and I/O signal grounding.
PCM data output in 8 channels.
Serial audio sample relative to the DA-BCK clock.
PCM left/right clock. Identifies the channel for each audio sample. The polarity is
programmable.
PCM bit clock. Obtained by dividing DA-XCK by 8. DA-BCK takes a value of 48 or 32 times
the sampling clock.
2.5 V supply voltage for the core logic.
Audio master frequency clock, which is used to generate DA-BCK and DALRCK. DA-XCK
takes a value of 384 or 256 times the sampling frequency.
Core logic and I/O signal grounding.
PCM input data with 2 channels. Serial audio sample relative to the DA-BCK clock.
PCM input left/right clock.
PCM input bit clock.
Programmable I/O pin, which enters input mode after resetting.
Input selection: Internal = VDD. External = VSS.
3.3 V analog supply voltage.
Video clock. Data is recorded at input.
System clock. The decoder requires an external 27 MHz TTL oscillator. Same drive
frequency as the VCK of 27 MHz.
Analog grounding of the PLL.
Serial CD data. This pin is also used as a DVD compression data pin DVD-DATA0.
3.3 V supply voltage for I/O signals.
16-bit word sync with programmable polarity for the decoder (right channel High).
This pin is also used as a DVD compression data pin DVD-DATA1.
Core logic and I/O signal grounding.
CD bit clock. The decoder accepts multiple BCK rates. This pin is also used as a DVD
compression data pin DVD-DATA2.
Performs High expression by indicating the damaged byte. The decoder holds the effective
pixels in the last image until the next effective image is decoded.
DVD compression data pin DVD-DATA3.
-
O
-
O
I/O
O
I/O
I/O
I/O
O
-
O
-
O
O
O
-
I/O
-
I
I
I
I/O
I
-
I
I
-
I
-
I
-
I
I
VDD-3.3
VDATA4
VSS
VDATA5
PIO7
VDATA6
VDATA7
PIO8
HSYNC
VSYNC
DA-IEC
VDD-3.3
DA-DATA0
VSS
DA-DATA1
DA-DATA2
DA-DATA3
DA-LRCK
DA-BCK
VDD-2.5
DA-XCK
VSS
DAI-DATA
DAI-LRCK
DAI-BCK
PIO9
CLKSEL
A-VDD
VCLK
SYSCLK
A-VSS
DVD-DATA0
/CD-DATA
VDD-3.3
DVD-DATA1
/CD-LRCK
VSS
DVD-DATA2
/CD-BCK
DVD-DATA3
/CD-C2PO
Pin No.
Symbol
I/O
Function
