TH-A9
1-30
MN67706ZY(IC201) : ADSC
1.Pin layout
CHCK40
DAT3
DAT2
DAT1
DAT0
33VSS
33VDD
TX
XRESET
ENS
ENC
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
MONA
MONB
MONC
NC
25VSS
25VDD
TSTSG
BDO
SYSCLK
OFTR
33VDD
33VSS
FBAL
TBAL
TGBAL
AVSS
ROUT
LOUT
AVDD
JLINE
DBALO
VCOF
TRCRS
CMPIN
LPFOUT
LPFIN
AVSS
LDCUR(AD6)
TDOFS(AD5)
TG(AD4)
RFENV(AD3)
HPFOUT
HPFIN
AVDD
VFOSHORT
33VDD
33VSS
TEST
MINTEST
NCLDCK/JUMP
SUBC
IPFLAG
DACCLK
NTRON
DACDATA/LG
DACLRCK/JMPINH
IDHOLD
SBCK/PLLOK
BLKCK/CPDET1
LRCK/CPDET2
IDGT/TEMUTE
DTRD
25VDD
25VSS
TILTN
TILT
AS(AD2)
TE(AD1)
FE(AD0)
AVDD
FODRV(DA1)
TRDRV(DA0)
AVSS
ARF
NARF
IREF1
IREF2
DSLF1
DSLF2
AVDD
VHALF
PLPG
PLFG
VREFH
RVI
AVSS
PLFLT1
TILTP
FG
SPDRV
TRSDRV
PLFLT2
JITOUT
RFDIF
CSLFL1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MN67706ZY
Traverse drive (DRVIC)
Spindle drive output (DRVIC)
FG signal input (spindle motor driver)
Connect with TP205
Connect with TP206
Connect with TP207
For internal core GND
Power supply for internal core (2.5V)
Data read control signal (ODC)
Pull down for GND
LR channel data strobe (ODC)/
CD sub code synchronize signal (ODC)/
CD sub-code data shift clock (ODC)/SYNC detection
Pull down for GND
1 bit DAC-LR channel data strobe (ODC)/
CD1 bit DAC channel data (ODC)
L:tracking ON (ODC)
1 bit DAC channel data shift clock (ODC)
CIRC error flag (ODC)
CD sub code (ODC)
CD sub code data frame clock (ODC)/DVD JUMP signal (ODC)
Connects with DVSS (for MINTEST)
Connects with DVSS (for TEST)
For I/O GND
Power supply for I/O (3.3V)
For SRDATA clock (ODC)
SRDATA3(ODC)
SRDATA2(ODC)
SRDATA1(ODC)
SRDATA0(ODC)
For I/O GND
Power supply for I/O (3.3V)
Digital audio interface
Reset L : Reset
Servo DSC sereal I/F chip select (SYSCON)
CIRC sereal I/F chip select (SYSCON)
Interrupt request to silicon (SYSCON)
Silicon cereal I/F clock (SYSCON)
Silicon cereal I/F data input (SYSCON)
Silicon cereal I/F data output (SYSCON)
Monitor terminal A (connect with TP226)
Monitor terminal B (connect with TP225)
Monitor terminal C (connect with TP224)
Not used (connect with TP211)
For internal core GND
Power supply for internal core (2.5V)
Tangential Phase difference (FEP)
RFENV (FEP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin No.
Pin No.
Symbol
Symbol
I/O
I/O
Function
Function
2.Pin function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AS(AD2)
TE(AD1)
FE(AD0)
AVDD
FODRV(DA1)
TRDRV(DA0)
AVSS
ARF
NARF
IREF1
IREF2
DSLF1
DSLF2
AVDD
VHALF
PLPG
PLFG
VREFH
RVI
AVSS
PLFLT1
PLFLT2
JITOUT
RFDIF
CSLFL1
VFOSHORT
AVDD
HPFIN
HPFOUT
AVSS
LPFIN
LPFOUT
CMPIN
TRCRS
VCOF
DBALO
JLINE
AVDD
LOUT
ROUT
AVSS
TGBAL
TBAL
FBAL
33VSS
33VDD
OFTR
SYSCLK
BDO
TSTSG
I
I
I
-
O
O
-
I
I
I
I
I/O
I/O
-
I
-
-
I
I/O
-
O
O
I/O
I
I/O
O
-
I
O
-
I
O
I
I
I/O
O
O
-
O
O
-
O
O
O
-
-
I
I
I
O
AS : All added signal (FEP)
Tracking error (FEP)
Focus error (FEP)
Power supply for analog circuit (3.3V)
Focus drive (DRVIC)
Tracking drive (DRVIC)
Ground for analog circuit
Equalized RF+(FEP)
Equalized RF–(FEP)
Reference power supply 1 for DBAL
Reference power supply 2 for DBAL
Capacitor 1 for DSL
Capacitor 2 for DSL
Power supply for analog circuit (3.3V)
Reference voltage 1.65±0.1V(FEP)
Not used
Not used
Reference voltage 2.2V±0.1V(FEP)
VREFH reference power supply for resistor
Ground for analog circuit
Capacitor 1 for PLL
Capacitor 2 for PLL
Detection signal output of jitter
Not used
Pull up for VHALF
VFO short output
Power supply for analog circuit (3.3V)
Pull up for VHALF
Connect woth TP208
Ground for analog circuit
Pull up for VHALF
Not used
Connect with TP210
Track crossing signal (FEP)
JFVCO control voltage
DSL balance adjustment output
J-line preset output (FEP)
Power supply for analog circuit (3.3V)
Connect with TP203 (analog audio L out)
Connect with TP204 (analog audio R out)
Ground for analog circuit
Tangential balance (FEP)
Tracking balance (FEP)
Focus balance (FEP)
For I/O GND
Power supply for I/O (3.3V)
Off-track error signal (FEP)
16.9344MHz system clock input (ODC)
BDO + BCA (FEP)
Self calibration signal (FEP)
TRSDRV
SPDRV
FG
TILTP
TILT
TILTN
25VSS
25VDD
DTRD
IDGT/TEMUTE
LRCK/CPDET2
BLKCK/CPDET1
SBCK/PLLOK
IDHOLD
DACLRCK/JMPINH
DACDATA/LG
NTRON
DACCLK
IPFLAG
SUBC
NCLDCK/JUMP
MINTEST
TEST
33VSS
33VDD
CHCK40
DAT3
DAT2
DAT1
DAT0
33VSS
33VDD
TX
XRESET
ENS
ENC
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
MONA
MONB
MONC
NC
25VSS
25VDD
LDCUR(AD6)
TDOFS(AD5)
TG(AD4)
RFENV(AD3)
O
O
I
O
O
O
-
-
I
I
O
O
I
I
I
I
O
O
O
O
O
I
I
-
-
O
O
O
O
O
-
-
O
I
I
I
O
I
I
O
O
O
O
O
-
-
I
I
I
I
