JVC TH-A9, Руководство по обслуживанию

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TH-A9
1-38
ZIVA3-PEO (3/5)
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Memory address.
3.3 V supply voltage for I/O signals.
Memory address.
Core logic and I/O signal grounding.
Memory address.
3.3 V supply voltage for I/O signals.
Memory address.
Core logic and I/O signal grounding.
Memory address.
3.3 V supply voltage for I/O signals.
No connection.
Core logic and I/O signal grounding.
No connection.
2.5 V supply voltage for the core logic.
No connection.
Core logic and I/O signal grounding.
No connection.
3.3 V supply voltage for I/O signals.
No connection.
Core logic and I/O signal grounding.
No connection.
The signal for opening the drain should be pulled up from 4.7 V to 3.3 V.
Programmable I/O pin. Enters input mode after resetting.
No connection.
Coupled with VSS or VDD-3.3.
Programmable I/O pin, which enters input mode after resetting
3.3 V supply voltage for I/O signals.
Coupled with VSS or VDD-3.3.
Core logic and I/O signal grounding.
Coupled with VSS or VDD-3.3.
Programmable I/O pin, which enters input mode after resetting.
Coupled with VSS or VDD-3.3.
Programmable I/O pin, which enters input mode after resetting.
Video data bus for byte-serial CbYCrY data in sync with VCLK. In power up, the decoder
does not drive VDATA. In boot-up, the decoder uses the configuration parameters for drive
or tri-state VDATA.
2.5 V supply voltage for the core logic.
Video data bus for byte-serial CbYCrY data in sync with VCLK. In power up, the decoder
does not drive VDATA. In boot-up, the decoder uses the configuration parameters for drive
or tri-state VDATA.
Core logic and I/O signal grounding.
Programmable I/O pin, which enters input mode after resetting.
Video data bus for byte-serial CbYCrY data in sync with VCLK. In power up, the decoder
does not drive VDATA. In boot-up, the decoder uses the configuration parameters for drive
or tri-state VDATA.
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
O
I/O
O
I
I/O
-
I
-
I
I/O
I
I/O
O
-
O
-
I/O
O
MADDR8
MADDR10
VDD-3.3
MADDR7
VSS
MADDR0
MADDR6
MADDR1
VDD-3.3
MADDR5
VSS
MADDR2
MADDR4
MADDR3
VDD-3.3
NC
VSS
NC
VDD-2.5
NC
VSS
NC
VDD-3.3
NC
VSS
NC
RESERVED
PIO2
NC
RESERVED
PIO3
VDD-3.3
RESERVED
VSS
RESERVED
PIO4
RESERVED
PIO5
VDATA0
VDATA1
VDD-2.5
VDATA2
VSS
PIO6
VDATA3
Pin No. Symbol I/O Function