Preface
Publication 21555, Rev. E, September 2002
vii
Illustrations
Figure 1-1:
Instrument Linearity ..................................................................................................... 1-6
Figure 2-1:
Setting the Logical Address ......................................................................................... 2-2
Figure 2-2:
Default Bus Arbitration Settings ................................................................................... 2-3
Figure 2-3:
SCPI Subsystem Model............................................................................................... 2-5
Figure 2-4:
CALCulate Subsystem Commands ............................................................................. 2-8
Figure 2-5:
SENSe Subsystem Command Tree ............................................................................ 2-9
Figure 2-6:
TRIGger Subsystem Command Tree ........................................................................ 2-11
Figure 2-7:
TRIGger Subsystem Command Tree ........................................................................ 2-21
Figure 2-8:
VPROPF Configuration.............................................................................................. 2-29
Figure 2-9:
SCPI Status Structure Registers ............................................................................... 2-41
Figure 3-1:
VXI Power Meter System Block Diagram .................................................................... 3-1
Figure 3-2:
Analog PC Assembly Block Diagram........................................................................... 3-2
Figure 3-3:
Calibrator Internal Power Standard Configuration ....................................................... 3-4
Figure 3-4:
Digital PC Assembly (A2) Block Diagram .................................................................... 3-8
Figure 3-5:
VXI Processor (A3) Block Diagram.............................................................................. 3-9
Figure 4-1:
Calibrator Reference Level Test Setup........................................................................ 4-2
Figure 4-2:
GPIB Port Test Setup .................................................................................................. 4-8
Figure 4-3:
Power Sensor Linearity Test Setup ........................................................................... 4-11
Figure B-1:
80401A Modulation-Related Uncertainty ..................................................................... B-7
Figure B-1:
Power Sensor Calibration Setup................................................................................ B-12
Содержание 58542
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