58452 VXIbus Universal Power Meter
3-8
Publication 21555, Rev. E, September 2002
3.5
Digital PC Board (A2)
I/O address decoding is done first in the PAL (U10), and secondarily in U2. During valid I/O addressing,
wait states are generated. The PAL monitors a clock cycle count (from U7A) to hold off DTACK on the
CPU. W1 is jumpered to four wait states. During ROM and RAM accesses, the PAL asserts DTACK
immediately with no wait states.
DTACK is passed back to the VXI Processor board. U12A provides an open collector signal.
RAM bank 1 is connected to the battery. When power is lost, U6 de-selects RAM bank 1 and connects
Vcc to the battery. This bank is then non-volatile and can be used for data storage. C24 is in parallel
with the battery and allows it to be replaced without losing data. Battery current can be measured at R1,
TP1 and TP2. At 2
µ
A, the voltage across the test points should measure about 2 mV.
U8 acts as an 8-bit input port addressed at CSTRG to monitor the eight TTL trigger lines on the VXI
bus. The 58542 can trigger measurements either from these eight lines or from the TTL trigger BNC
input on the front panel.
The Digital board interfaces with the Analog board at J1. All digital lines are buffered (U3, U4 and U5),
and additional analog chip select decoding is done with U1.
U9A and U9B generate the upper data byte and lower data byte write signals. U11 buffers the R/*W and
Reset signals.
W2 jumpers the three interrupt signals from the Analog board to the VXI Processor board. These
jumpers should only be removed for troubleshooting.
Figure 3-4: Digital PC Assembly (A2) Block Diagram
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