GE Solar 8000M/i, Руководство по обслуживанию

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2-16 Solar 8000M/i patient monitor 2026265-075C
Equipment overview: Theory of operation
Core processing system
The core processing system of the processor board is the microprocessor,
the memory subsystem and the peripheral set.
The microprocessor
The Motorola PowerPC MPC860P, operating internally at 66.66 MHz
and 33.33 MHz externally, is the microprocessor used in the Solar
8000M/i processor PCB. The MPC860P consists of a PowerPC core with a
System Interface Unit (SIU) and Communications Processor Module
(CPM).
The main facilities integrated into the MPC860P include:
„
PowerPC Core including:
‹
16k of Dual ported RAM for registers and microcode
‹
A Memory Management Unit (MMU)
‹
16 kByte Instruction Cache
‹
8 kByte Data Cache
„
System Integration Unit (SIU) including:
‹
Memory Controller and Wait State Generator via Eight(8)
General Purpose Chip-Select Machines (GPCM) and two(2)
Universal Programmable Machines (UPM)
‹
Development Port/Background Debug Monitor
‹
System Configuration and Protections such as the Bus Monitor,
Software Watchdog Timer, and Periodic Interrupt Timer
‹
PLL Clock synthesizer
„
Communication Processor Module (CPM) including:
‹
One (1) Fast Ethernet Channel (Media Independent Interface)
‹
Four SCCs, all of which can do IEEE 802.3 Ethernet
‹
Two SMCs (UARTs)
‹
One SPI Interface
‹
One I2C Interface
‹
Seven IRQ lines
‹
I/O port pin banks, some of which can be programmed to
generate an interrupt when a condition is present
A Development Port, commonly referred to as a Background Debug
Monitor (BDM) debug port on other processors, is resident in the
MPC860 to assist in debugging and troubleshooting the processor
operation.
NOTE
The MPC860 is +5V I/O tolerant on all of its pins except for the clock
input. This is important because the signals from the TRAM-NET
Hub are +5V signal levels.