Fuji Electric Faldic-a RYS-R Series, Руководство пользователя

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5-15
MHT260a (Engl.)
(4) Origin LS detection (40)
Because the [LS] signal requires quick response, this should be directly input to the amplifier in general. When the host controller needs the
origin signal, the origin LS detection signal can be output.
While the [LS] signal is on, the origin LS detection signal (40) is on.
(5) LS-Z pulse
The encoder pulse count can be monitored, from the time when the [LS] signal goes to OFF level, until Z-phase signal is detected.
If this count is small, Z-phase signal of one rotation later may have been detected, depending on the origin LS response. In this case, move
the mechanical position of the origin LS.
5.4.2 Position preset
When this signal turns on, the current station number can be rewritten.
Position preset (Control input signal)
■
Function
At the ON edge(*) of this signal input, the current position can be rewritten to the value of the station mumber [PD14 to PD0].
Position preset is executable while speed zero [NZERO] signal is on.
When the position preset is executed, the origin return end is on.
This signal can reset the following alarm detection:
1) ABS (absolute) data lost
■
Parameter setting
To allocate the position preset signal to the control input terminal, set (16) to the system para.. If this signal is not allocated to the control
input terminal, this signal is deemed "always off".
Note : (*) ON edge means the control input signal's transfer point from off to on.
Origin LS [LS] detection
Origin LS (origin limit switch)
APS30
APS30 APS30
APS30
PWR PWR PWR PWR
ALM ALM ALM ALM
ＳＸ
ＳＸ ＳＸ
ＳＸ
SCPU32
SCPU32 SCPU32
SCPU32
LOADER LOADER LOADER LOADER
RUN
RUN RUN
RUN
TERM TERM TERM TERM
SLV
SLV SLV
SLV
STOP
STOP STOP
STOP
CPU CPU CPU CPU
No. No. No. No.
ONL
ONL ONL
ONL
ERR
ERR ERR
ERR
RUN RUN RUN RUN
ALM
ALM ALM ALM
BAT
BAT BAT
BAT
ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7
ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415
ONL CH1 ONL CH1 ONL CH1 ONL CH1
ERR CH2
ERR CH2 ERR CH2
ERR CH2
EMG +OT ‑OT EMG +OT ‑OT EMG +OT ‑OT EMG +OT ‑OT
20
20 20
20
1 11 1
B/A
B/A B/A
B/A
HP2
HP2 HP2
HP2
ONL ONL ONL ONL
ERR ERR ERR ERR
PE1
PE1 PE1
PE1
PH
PH PH
PH
PL PL PL PL
DA DA DA DA
CH CH CH CH
No.
No. No.
No.
SCPU32
SCPU32 SCPU32
SCPU32
LOADER LOADER LOADER LOADER
RUN
RUN RUN
RUN
TERM TERM TERM TERM
SLV
SLV SLV
SLV
STOP
STOP STOP
STOP
CPU CPU CPU CPU
No. No. No. No.
ONL
ONL ONL
ONL
ERR
ERR ERR
ERR
RUN RUN RUN RUN
ALM
ALM ALM ALM
BAT
BAT BAT
BAT
ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7
ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415
K80791234
K80791234 K80791234
K80791234
L1 L1 L1 L1
L2 L2 L2 L2
L3 L3 L3 L3
DB DB DB DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V VV V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS
RYS20 1 S3-VVS RYS20 1 S3-VVS
RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC ESC ESC ESC
K80791234
K80791234 K80791234
K80791234
L1 L1 L1 L1
L2 L2 L2 L2
L3 L3 L3 L3
DB DB DB DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V VV V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS
RYS20 1 S3-VVS RYS20 1 S3-VVS
RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC ESC ESC ESC