Fuji Electric Faldic-a RYS-R Series, Руководство пользователя

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5-3
MHT260a (Engl.)
■
Parameter setting
To allocate the [RUN] signal to the control input terminal, set (1) to the system para.(*). If this signal is not allocated to the control input
terminal, this signal is deemed "always off".
■
Related item
For the [EMG] signal, see 5.6.1 Forced stop [EMG]/Forced stop detection.
5.2.2 Ready [RDY]
This signal turns on when the motor can be rotated.
Ready [RDY] (Control output signal)
■
Function
Listed below are five conditions for turning on this signal.
1) Run command [RUN] (1) signal on
2) Forced stop [EMG] (10) signal on
3) Alarm detection (16) signal off
4) External fault input (34) signal on
5) Free-run [BX] (54) signal off
When the host controller receives the on/off status of [RDY] signal, it recognizes that the motor can be rotated.
■
Parameter setting
To allocate the [RDY] signal to the control output terminal, set (1) to the system para..
■
Related item
The amplifier can output the CPU ready [CPURDY] (28) signal, which is turned on when the power is being supplied to amplifier and the
internal CPU is processing normally.
5.2.3 Alarm reset [RST]
This signal input resets the alarm detection from the amplifier.
Alarm reset [RST] (Control input signal)
■
Function
At the ON edge of [RST] signal of control input signals, the alarm detection can be reset.
Alarm detection can also be reset in the test running mode [
] by keypad panel.
Alarm detection can also be reset by turning on power supply again.
■
Parameter setting
To allocate the [RST] signal to the control input terminal, set (11) to the system para. If this signal is not allocated to the control input
terminal, this signal is deemed "always off".
Note: (*) para.: parameter
A P S 3 0
A P S 3 0 A P S 3 0
A P S 3 0
P W R
P W R P W R
P W R
A L M A L M A L M A L M
ＳＸ
ＳＸ ＳＸ
ＳＸ
S C P U 3 2 S C P U 3 2 S C P U 3 2 S C P U 3 2
L O A D E R L O A D E R L O A D E R L O A D E R
RUN RUN RUN RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP
STOP STOP
STOP
CPU CPU CPU CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN
RUN RUN
RUN
ALM
ALM ALM ALM
BAT
BAT BAT
BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
O N L C H 1 O N L C H 1 O N L C H 1 O N L C H 1
E R R C H 2
E R R C H 2 E R R C H 2
E R R C H 2
E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T E M G + O T ‑ O T
2 0 2 0 2 0 2 0
1
11
1
B / A B / A B / A B / A
H P 2
H P 2 H P 2
H P 2
O N L O N L O N L O N L
E R R
E R R E R R
E R R
P E 1
P E 1 P E 1
P E 1
P H P H P H P H
P L P L P L P L
D A
D A D A
D A
C H C H C H C H
N o .
N o . N o . N o .
S C P U 3 2 S C P U 3 2 S C P U 3 2 S C P U 3 2
L O A D E R L O A D E R L O A D E R L O A D E R
RUN RUN RUN RUN
TERM TERM TERM TERM
SLV SLV SLV SLV
STOP
STOP STOP
STOP
CPU CPU CPU CPU
No. No. No. No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN
RUN RUN
RUN
ALM
ALM ALM ALM
BAT
BAT BAT
BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
K80791543
K80791543 K80791543
K80791543
L1
L1 L1
L1
L2 L2 L2 L2
L3 L3 L3 L3
DB DB DB DB
P1 P1 P1 P1
N NN N
P+ P+ P+ P+
U
UU
U
V VV V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS40 1 S3-LPS RYS40 1 S3-LPS RYS40 1 S3-LPS RYS40 1 S3-LPS
MODE MODE MODE MODE
ESC ESC ESC ESC
Run command [RUN]
Ready [RDY]