Fuji Electric Faldic-a RYS-R Series, Руководство пользователя

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5-11
MHT260a (Engl.)
5.3.5 Deviation excessive [OF]
This function sets the deviation amount of deviation excessive (alarm detection) of amplifier.
Sets the pulse count for alarm detection about [OF]. Initial value at factory setting is 10000, and detects the deviation amount with 1000000
[pulse]. At factory setting, [OF] is detected, when the difference (deviation) between the current command position and current feedback
position becomes approximately 15.2 [revolution] when converted to motor rotation.
■
Parameter setting
The deviation excessive width is setting for use with alarm detection, and cannot be assigned to control output terminal.
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Related items
Basic parameter 54
Para. Name Setting range Initial value Change
54 Deviation excessive width 10 to 65535 (in 1 step)
[x 100 pulse] 10000 Always
Setting is made by encoder pulse count (65536 [pulse/rev]).
5.3.6 Speed zero [NZERO]
This signal is turned on when the motor speed is near zero.
Speed zero [NZERO] (Control output signal)
■
Function
This signal turns on when the motor speed is below the value set by basic para. 52.
■
Parameter setting
To allocate the [NZERO] signal to the control output terminal, set (24) to the system para..
5.3.7 Speed arrive [NARV]
Check can be done that the motor rotation reaches the command speed.
Speed arrive [NARV] (Control output signal)
■
Function
This signal turns on, when motor speed reaches within setting value of basic para. 51 from the command speed. The command speed
involves speed setting by para., speed data from positioning data and speed command voltage.
APS30 APS30 APS30 APS30
PWR PWR PWR PWR
ALM ALM ALM ALM
ＳＸ
ＳＸ ＳＸ
ＳＸ
SCPU32 SCPU32 SCPU32 SCPU32
LOADER
LOADER LOADER
LOADER
RUN RUN RUN RUN
TERM
TERM TERM
TERM
SLV SLV SLV SLV
STOP STOP STOP STOP
CPU CPU CPU CPU
No.
No. No.
No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN
RUN RUN
RUN
ALM ALM ALM ALM
BAT BAT BAT BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
O N L C H 1 O N L C H 1 O N L C H 1 O N L C H 1
E R R C H 2
E R R C H 2 E R R C H 2
E R R C H 2
E M G + O T ‑ O T
E M G + O T ‑ O T E M G + O T ‑ O T
E M G + O T ‑ O T
2 0
2 0 2 0
2 0
1 11 1
B / A B / A B / A B / A
HP2 HP2 HP2 HP2
O N L O N L O N L O N L
E R R
E R R E R R
E R R
PE1 PE1 PE1 PE1
PH PH PH PH
PL
PL PL
PL
DA DA DA DA
C H C H C H C H
N o .
N o . N o . N o .
SCPU32 SCPU32 SCPU32 SCPU32
LOADER
LOADER LOADER
LOADER
RUN RUN RUN RUN
TERM
TERM TERM
TERM
SLV SLV SLV SLV
STOP STOP STOP STOP
CPU CPU CPU CPU
No.
No. No.
No.
ONL ONL ONL ONL
ERR
ERR ERR
ERR
RUN
RUN RUN
RUN
ALM ALM ALM ALM
BAT BAT BAT BAT
O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7 O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5 E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
K80791234 K80791234 K80791234 K80791234
L1
L1 L1
L1
L2 L2 L2 L2
L3 L3 L3 L3
DB DB DB DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V
VV
V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC ESC ESC ESC
K80791234 K80791234 K80791234 K80791234
L1
L1 L1
L1
L2 L2 L2 L2
L3 L3 L3 L3
DB DB DB DB
P1
P1 P1
P1
N NN N
P+ P+ P+ P+
U UU U
V
VV
V
W WW W
CHARGE CHARGE CHARGE CHARGE
FALDIC FALDIC FALDIC FALDIC
SHIFT SHIFT SHIFT SHIFT
ENT ENT ENT ENT
RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS RYS20 1 S3-VVS
MODE MODE MODE MODE
ESC ESC ESC ESC
Speed zero [NZERO]