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5-4
MHT260a (Engl.)
■
Related item
Resetting method of the alarm detection is as listed below:
1) At the ON edge of [RST] signal of control input signal
2) ENT key operation in the test running mode [
]
3) Press
∧
key and
∨
key simultaneously (longer than 1 [s]) at alarm detection [
].
4) Press
∧
key and
∨
key simultaneously (longer than 1 [s]) at alarm history [
].
5) Turn power off and turn on again
To initialize the history [
] of alarm detection, press ENT key in the test running mode.
5.2.4 Alarm detection [ALM]
This signal is turned on, when the amplifier protective function is activated (detects an alarm).
Alarm detection [ALM] (Control output signal)
■
Function
This signal is on when amplifier detects alarm, and retained by amplifier. The signal is turned off at the ON edge of alarm reset [RST] signal
after the cause of alarm is removed (Motor running is enable).
Alarm or no alarm can be recognized, when the host controller receives the on/off status of the [ALM] signal. This also can be recognized
whether the ready [RDY] signal is off when the run command [RUN] is on.
■
Parameter setting
To allocate the [ALM] signal to the control output terminal, set (16) to the system para..
■
Related item
The contents of alarm detection can also be outputted to the control output terminals by alarm code.
Alarm code 4 [ALM4] (36) Alarm code 3 [ALM3] (35)
Alarm code 2 [ALM2] (34) Alarm code 1 [ALM1] (33)
Alarm code 0 [ALM0] (32)
For SX bus type (SX bus direct connection), alarm code is outputted at +5 word position of IQ area.
For T-link type (T-link direct connection), alarm code is outputted at +1 word position of WB area.
K80791234
K80791234
K80791234
K80791234
L1
L1
L1
L1
L2
L2
L2
L2
L3
L3
L3
L3
DB
DB
DB
DB
P1
P1
P1
P1
N
NN
N
P+
P+
P+
P+
U
UU
U
V
VV
V
W
WW
W
CHARGE
CHARGE
CHARGE
CHARGE
FALDIC
FALDIC
FALDIC
FALDIC
SHIFT
SHIFT
SHIFT
SHIFT
ENT
ENT
ENT
ENT
RYS20
1
S3-VVS
RYS20
1
S3-VVS
RYS20
1
S3-VVS
RYS20
1
S3-VVS
MODE
MODE
MODE
MODE
ESC
ESC
ESC
ESC
K80791234
K80791234
K80791234
K80791234
L1
L1
L1
L1
L2
L2
L2
L2
L3
L3
L3
L3
DB
DB
DB
DB
P1
P1
P1
P1
N
NN
N
P+
P+
P+
P+
U
UU
U
V
VV
V
W
WW
W
CHARGE
CHARGE
CHARGE
CHARGE
FALDIC
FALDIC
FALDIC
FALDIC
SHIFT
SHIFT
SHIFT
SHIFT
ENT
ENT
ENT
ENT
RYS20
1
S3-LPS
RYS20
1
S3-LPS
RYS20
1
S3-LPS
RYS20
1
S3-LPS
MODE
MODE
MODE
MODE
ESC
ESC
ESC
ESC
APS30
APS30
APS30
APS30
PWR
PWR
PWR
PWR
ALM
ALM
ALM
ALM
SX
SX
SX
SX
SCPU32
SCPU32
SCPU32
SCPU32
LOADER
LOADER
LOADER
LOADER
RUN
RUN
RUN
RUN
TERM
TERM
TERM
TERM
SLV
SLV
SLV
SLV
STOP
STOP
STOP
STOP
CPU
CPU
CPU
CPU
No.
No.
No.
No.
ONL
ONL
ONL
ONL
ERR
ERR
ERR
ERR
RUN
RUN
RUN
RUN
ALM
ALM
ALM
ALM
BAT
BAT
BAT
BAT
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
O N L C H 1
O N L C H 1
O N L C H 1
O N L C H 1
E R R C H 2
E R R C H 2
E R R C H 2
E R R C H 2
E M G + O T ‑ O T
E M G + O T ‑ O T
E M G + O T ‑ O T
E M G + O T ‑ O T
2 0
2 0
2 0
2 0
1
11
1
B / A
B / A
B / A
B / A
HP2
HP2
HP2
HP2
O N L
O N L
O N L
O N L
E R R
E R R
E R R
E R R
PE1
PE1
PE1
PE1
PH
PH
PH
PH
PL
PL
PL
PL
DA
DA
DA
DA
C H
C H
C H
C H
N o .
N o .
N o .
N o .
SCPU32
SCPU32
SCPU32
SCPU32
LOADER
LOADER
LOADER
LOADER
RUN
RUN
RUN
RUN
TERM
TERM
TERM
TERM
SLV
SLV
SLV
SLV
STOP
STOP
STOP
STOP
CPU
CPU
CPU
CPU
No.
No.
No.
No.
ONL
ONL
ONL
ONL
ERR
ERR
ERR
ERR
RUN
RUN
RUN
RUN
ALM
ALM
ALM
ALM
BAT
BAT
BAT
BAT
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
O N L 0 1 2 3 4 5 6 7
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
E R R 8 9 1 0 1 1 1 2 1 3 1 4 1 5
Alarm detection [ALM]
Содержание Faldic-a RYS-R Series
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