Freescale Semiconductor PXR4030, Справочное руководство

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Resets
PXR40 Microcontroller Reference Manual, Rev. 1
4-6 Freescale Semiconductor
4.5.1 Power-on Reset (POR)
The internal power-on reset signal is asserted when either the supply voltages, nominally 3.3V (VDD33)
and 1.2V (VDD) or the RESET supply (VDDEH1) fall below defined threshold voltages. See the device
data sheet for the specifications of these thresholds. The PMC provides additional software-configurable
registers for masking of POR assertions based on these and additional supplies. See the PMC chapter for
details. Although assertion of the power-on reset signal causes reset, the RESET pin must be asserted
during a power-on reset to guarantee proper operation of the MCU.
The system clock source is determined during reset as shown in Table 6-13 (FMPLL chapter). The value
of the PLLCFG[0:1] pins are latched during reset. If PLLCFG[0:1] are changed during a reset other than
power-on reset, the internal clocks may glitch as the clock source is changed between PLL Off mode and
PLL clock mode or from one PLL clock mode to another. Whenever PLLCFG[0:1] are changed in reset
to a value other than what it was before the reset, an immediate loss of lock condition is declared. This
only applies if the PLL was running in a locked state prior to the assertion of reset and change of
PLLCFG[0:1].
The signal on the WKPCFG pin determines whether weak pull up or pull down devices are enabled after
reset on the eTPU and eMIOS pins. The WKPCFG pin is applied on the assertion of the internal reset
signal (assertion of RSTOUT). See
Section 4.7.3, Reset Weak Pull Up/Down Configuration , for more
information.
Once the RESET input pin is negated the reset controller checks the FMPLL Loss of Lock reset request
signal. The internal reset signal and RSTOUT are kept asserted until the FMPLL negates the Loss of Lock
reset request signal. After the Loss of Lock reset request signal is negated, the reset controller waits for a
predetermined number of clock cycles (refer to
Section 4.3.2, RSTOUT ) before negating the RSTOUT
pin. The reset configuration pins are sampled 4 clock cycles before the negation of RSTOUT, and the
associated bits/fields are updated in the SIU_RSR. In addition, the PORS and ERS bits are set, and all other
reset status bits are cleared in the Reset Status Register.
4.5.2 External Reset
When the reset controller detects assertion of the RESET pin, the internal reset signal and RSTOUT pin
are asserted. The values on the WKPCFG pin and PLLCFG pins are applied at the assertion of the internal
reset signal (assertion of RSTOUT). Once the RESET pin is negated and the FMPLL Loss of Lock reset
request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to
Section 4.3.2, RSTOUT ). Once the clock count finishes, the reset configuration pins are latched. The reset
controller then waits 4 clock cycles before negating RSTOUT, and the associated bits/fields are updated
in the SIU_RSR. In addition, the ERS bit is set, and all other reset status bits in the SIU_RSR are cleared.
4.5.3 Loss of Lock
A Loss of Lock Reset occurs when the FMPLL loses lock and the Loss of Lock Reset Enable (LOLRE)
bit in the FMPLL Synthesizer Control Register (ESYNCR2) is set. The internal reset signal and RSTOUT
pin are asserted. The values on the WKPCFG and PLLCFG pins are applied at the assertion of the internal
reset signal (assertion of RSTOUT). Once the FMPLL Loss of Lock reset request signal is negated, the
reset controller waits for a predetermined number of clock cycles (refer to
Section 4.3.2, RSTOUT ). Once