Freescale Semiconductor PXR4030, Справочное руководство

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External Bus Interface (EBI)
Freescale Semiconductor 30-41
PXR40 Microcontroller Reference Manual, Rev. 1
Table 30-18 lists the patterns of the data transfer for write cycles when accesses are initiated by the MCU.
The bytes indicated as ‘—’ are not driven during that write cycle.
30.4.2.8 Termination Signals Protocol
The termination signals protocol was defined in order to avoid electrical contention on lines that can be
driven by various sources. In order to do that, a slave must not drive signals associated with the data
transfer until the address phase is completed and it recognizes the address as its own. The slave must
disconnect from signals immediately after it acknowledges the cycle and not later than the termination of
the next address phase cycle.
For EBI-mastered non-chip-select accesses, the EBI requires assertion of D_TA from an external device
to signal that the bus cycle is complete. The EBI uses a latched version of D_TA (1 cycle delayed) for these
accesses to help make timing at high frequencies. This results in the EBI driving the address and control
signals 1 cycle longer than required, as seen in
Figure 30-33 . However, the D_ADD_DAT does not need
to be held 1 cycle longer by the slave, because the EBI latches D_ADD_DAT every cycle during
non-chip-select accesses. During these accesses, the EBI does not drive the D_TA signal, leaving it up to
an external device (or weak internal pullup) to drive D_TA.
For EBI-mastered chip-select accesses, when the SETA bit is 0, the EBI drives D_TA the entire cycle,
asserting according to internal wait state counters to terminate the cycle. When the SETA bit is 1, the EBI
samples the D_TA for the entire cycle. During idle periods on the external bus, the EBI drives D_TA
negated as long as it is granted the bus; when it no longer owns the bus, it lets go of D_TA.
1
Also applies when DBM=1 for 16-bit data bus mode.
2
For address/data muxed transfers, D_ADD_DAT[16:23] are used externally, not D_ADD_DAT[0:7].
3
For address/data muxed transfers, D_ADD_DAT[24:31] are used externally, not D_ADD_DAT[8:15].
4
This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and
OP3.
Table 30-18. Data Bus Contents for Write Cycles
Transfer
Size
Address 32-Bit Port Size 16-Bit Port Size
1
1
Also applies when DBM=1 for 16-bit data bus mode.
A30 A31 D0:D7 D8:D15 D16:D23 D24:D31 D0:D7
2
2
For address/data muxed transfers, D_ADD_DAT[16:23] are used externally, not D_ADD_DAT[0:7].
D8:D15
3
3
For address/data muxed transfers, D_ADD_DAT[24:31] are used externally, not D_ADD_DAT[8:15].
Byte
0 0 OP0 — — — OP0 —
0 1 OP1 OP1 — — — OP1
1 0 OP2 — OP2 — OP2 —
1 1 OP3 OP3 — OP3 — OP3
16-bit
0 0 OP0 OP1 — — OP0 OP1
1 0 OP2 OP3 OP2 OP3 OP2 OP3
32-bit
0 0 OP0 OP1 OP2 OP3 OP0 or OP2
4
4
This case consists of two 16-bit external transactions, the first writing OP0 and OP1, the second writing OP2 and OP3.
OP1 or OP3