Freescale Semiconductor PXR4030, Справочное руководство

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Enhanced Time Processing Unit (eTPU2)
29-58 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 29-28. Priority Passing Example
Examples of priority passing are shown in Figure 29-28 . Each cycle contains seven time slots (or less if
no service request exist). In cycle B, no high-level or middle-level service requests are present before time
slot three which is assigned by default to high-level priority. Thus, time slot three is passed to the low level.
In cycle B there are also no middle-level service requests before time slot six, so it passes the priority to a
requesting high-level channel. During time slot six no more high level requests are left, but two new
middle-level requests arrive, and there are also three low level pending service requests. Thus, time slot
seven of cycle B and time slot one of cycle C are passed to the middle-level which is the next priority level
after high. Time slots two and three of cycle C are passed to the low level which contains the three
remaining channel service requests. At time slot three of cycle C the last low level request is serviced, and
the Scheduler passes to idle state. At this point the cycle C is truncated and the Scheduler passes to time
slot one of cycle D.
SLOT Number
6 7 1 2 3 4 5 6 1 2 3 1
M H H M H L H M H H M H H
High Pend Count
Service High
2 1
0 1 0
2 0
- X New Service Requests Arrive at a Specific Priority Level
2 0
X
2
2 2
1
1
1 0
0 0 1
2
2
1 0 2
2
7
DH DM DH H>L DL DH M>H DM H>M H>M M>L H>L
1
0
DH, DH, DL - Default Service High, Middle or Low
H>L, H>M, M>H, M>L - Priority Passing Scheme
ID - Idle (no service request)
ID
Slot Assignment
SLOT ASSIGNMENTS:
Reset Slot
Fixed Priority Level
Middle Pend Count
Service Middle
Low Pend Count
Service Low
Number
Cycle A
Cycle B
Cycle C (truncated)
Cycle D
2 3
M H
1
1
1
1
0 1
1
0
0
1
H
H>M
DM DH
1
H
ID