Freescale Semiconductor PXR4030, Справочное руководство

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General-Purpose Static RAM (SRAM)
11-2 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
11.4 Register Memory Map
The SRAM occupies 256 KB of memory starting at the base address as shown in Table 11-2 .
The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM. See
Chapter 17, Error Correction Status Module (ECSM) , for more information.
11.5 Functional Description
ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and
ECC calculations are performed during the write portion of a read/write (R/W) operation. Because the
ECC bits can contain random data after the device is powered on, you must initialize the SRAM by
executing 64-bit write instructions to the entire SRAM. For more information, see
Section 11.7,
Initialization and Application Information .
11.6 SRAM ECC Mechanism
The SRAM ECC detects the following conditions and produces the following results:
• Detects and corrects all 1-bit errors
• Detects and flags all 2-bit errors as non-correctable errors
• Detects 72-bit reads (64-bit data bus plus the 8-bit ECC) that return all zeros or all ones, asserts an
error indicator on the bus cycle, and sets the error flag
SRAM does not detect all errors greater than 2 bits. Internal SRAM writes are done on byte boundaries:
• 1 byte (0:7 bits)
• 2 bytes (0:15 bits)
• 4 bytes or 1 word (0:31 bits)
• 8 bytes or 2 words (0:63 bits)
If the entire 64 data bits are written to SRAM, no read operation is performed and the ECC is calculated
across the 64-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM. If the
write operation is less than the entire 64-bit data width (1-, 2-, or 4-byte segment), the following occurs:
1. The ECC mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or
flagging errors.
2. The write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data
bus.
3. The ECC is then calculated on the resulting 64 bits formed in the previous step.
4. The 8-bit ECC result is appended to the 64 bits from the data bus, and the 72-bit value is then
written to SRAM.
Table 11-2. SRAM Memory Map
Address Register Name Register Description Size
Base (0x4000_0000) — SRAM powered by V
STBY
32 KB
Base + 0x8000 — 224-KB RAM 224 KB