Freescale Semiconductor PXR4030, Справочное руководство

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FlexRay Communication Controller (FLEXRAY)
22-126 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
If the FIFO fill level FLA (FLB) is 0, than the FIFOA (FIFOB) contains no valid messages and the Receive
FIFO A Read Index Register (RFARIR) ( Receive FIFO B Read Index Register (RFBRIR) ) pointing to a
message buffer with invalid content. In this case the application must not read data from the FIFO.
To access the oldest message in the FIFOA (FIFOB), the application first reads the read index RDIDX out
of the
Receive FIFO A Read Index Register (RFARIR) ( Receive FIFO B Read Index Register (RFBRIR) ).
This read index points to the message buffer header field of the oldest message buffer that contains valid
received message data. The application can access the message data as described in
Section 22.6.3.3,
Receive FIFO. When the application has read the message buffer data and status information, it can update
the FIFO as described in Section 22.6.9.8, FIFO Update .
22.6.9.8 FIFO Update
The application updates the FIFOA (FIFOB) by writing a pop count value pc different from 0 to the
PCA (PCB) field in the Receive FIFO Fill Level and POP Count Register (RFFLPCR) .
As a result of the this operation, the controller removes the oldest pc entries from FIFOA (FIFOB).
If the specified pop count value pc is greater than the current fill level fl provided in FLA (FAB) field, then
only fl entries are removed from the FIFOA (FIFOB), the remaining fl-pc requested pop operations are
discarded without any notification. In this case FIFOA (FIFOB) is empty after the update operation.
The read index in the Receive FIFO A Read Index Register (RFARIR) ( Receive FIFO B Read Index
Register (RFBRIR) ) is incremented by the number of removed items. If the read index reaches the top of
the FIFO, it wraps around to the FIFO start index defined in Receive FIFO Start Index Register (RFSIR)
automatically.
22.6.9.8.1 FIFO Interrupt Flag Update
Th FIFO Interrupt Flag Update mode is configured, when the FIFO update mode flag MCR[FUM] is set
to 0. In this mode FIFOA (FIFOB) will be updated by 1 entry, when the interrupt flag GIFER[FAFAIF]
(GIFER[FAFBIF]) is written with 1 by the application.
If the FIFO is empty, the update request is ignored without any notification.
The read index in the Receive FIFO A Read Index Register (RFARIR) ( Receive FIFO B Read Index
Register (RFBRIR) ) is incremented by 1, if the FIFO was not empty. If the read index reaches the top of
the FIFO, it wraps around to the FIFO start index automatically.
22.6.9.9 FIFO Filtering
The FIFO filtering is activated after all enabled individual receive message buffers have been searched
without success for a message buffer to receive the current frame.
The controller provides three sets of FIFO filters. The FIFO filters are applied to valid non-null frames
only. The FIFO will not receive invalid or null-frames. For each FIFO filter, the pass criteria is specified
in the related section given below. Only frames that have passed all filters will be appended to the FIFO.
The FIFO filter path is depicted in
Figure 22-138 .