Freescale Semiconductor PXR4030, Справочное руководство

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Resets
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 4-3
pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH
input pins.
Figure 4-1 and Figure 4-2 show logic flows of the reset state machine on assertion of RESET.
4.3.2 RSTOUT
The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven
to the low state by the MCU for all internal and external reset sources.
If the PLL is configured for normal mode, the RSTOUT pin is asserted for 2400 clock cycles, plus 4 cycles
for sampling of the configuration pins. See
Table 4-3 for other source values.
The RSTOUT pin can also be asserted by a write to the SER bit of the System Reset Control Register
(SIU_SRCR); however no system reset occurs under this circumstance.
4.4 FMPLL Lock Gating Signal
The FMPLL Loss of Lock reset request is connected to both a reset request and a reset gating signal in the
SIU. The FMPLL asserts the Loss of Lock reset request until the PLL has achieved lock.
4.5 Reset Source Descriptions
For the following reset source descriptions refer to the reset flow diagrams in Figure 4-1 and Figure 4-2 .
Figure 4-1 shows the reset flow for assertion of the RESET pin. Figure 4-2 shows the internal processing
of reset for all reset sources.
Table 4-3. Clock Cycles for Different Reset Sources
Source Description
Number of clock cycles
(short count)
1
1
Used in the XOSC and XREF modes.
Number of clock cycles
(long count)
2
2
Used in the bypass and 1:1 modes.
SIU_POR Power On Reset 2400 16000
SIU_ER External Reset (RESET pin) 2410 16100
SIU_LLR Loss of Lock Reset 2420 16200
SIU_WTR Watchdog Timer Reset 2430 16300
SIU_CR Core Reset 2440 16400
SIU_SWTR Software Watchdog Timer Reset 2450 16500
SIU_LCR Loss of Clock Reset 2460 16600
SIU_SSR Software System Reset 2470 16700
SIU_SER Software External Reset 2480 16800