Epson S5U1C17001C, Руководство пользователя

Страница: 733 / 742

Reference
Opcode
jreq / jreq.d
sjreq / sjreq.d
xjreq / xjreq.d
jrne / jrne.d
sjrne / sjrne.d
xjrne / xjrne.d
call / call.d
scall / scall.d
xcall / xcall.d
calla / calla.d
scalla / scalla.d
xcalla / xcalla.d
ret / ret.d
int
intl
reti / reti.d
brk
retd
sr
sa
sl
swap
Operand
sign7
label
±
imm20
sign20
label
±
imm24
sign24
sign7
label
±
imm20
sign20
label
±
imm24
sign24
%rb
sign10
label
±
imm20
sign20
label
±
imm24
sign24
%rb
imm7
label
±
imm20
imm20
label
±
imm24
imm24
imm5
imm5, imm3
%rd, %rs
%rd, imm7
%rd, %rs
%rd, imm7
%rd, %rs
%rd, imm7
%rd, %rs
Function
pc
←
pc+2+sign8 if Z is true; sign8={sign7,0}
pc
←
label
±
imm20 if Z is true
pc
←
pc+2+sign20 if Z is true
pc
←
label
±
imm24 if Z is true
pc
←
pc+2+sign24 if Z is true
pc
←
pc+2+sign8 if !Z is true; sign8={sign7,0}
pc
←
label
±
imm20 if !Z is true
pc
←
pc+2+sign20 if !Z is true
pc
←
label
±
imm24 if !Z is true
pc
←
pc+2+sign24 if !Z is true
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
pc+2+rb
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
pc+2+sign11; sign11={sign10,0}
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
label
±
imm20
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
pc+2+sign20
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
label
±
imm24
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
pc+2+sign24
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
rb
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
imm7
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
label
±
imm20
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
imm20
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
label
±
imm24
sp
←
sp-4, A[sp]
←
pc+2(d=0)/4(d=1), pc
←
imm24
pc
←
A
[
sp](23:0), sp
←
sp+4
sp
←
sp-4, A[sp]
←
{psr, pc+2}, pc
←
vector(TTBR+imm5
×
4)
sp
←
sp-4, A[sp]
←
{psr, pc+2}, pc
←
vector(TTBR+imm5
×
4), psr(IL)
←
imm3
{psr, pc}
←
A[sp], sp
←
sp+4
A[DBRAM]
←
{psr, pc+2}, A[DBRAM+4]
←
r0, pc
←
0xfffc00
r0
←
A[DBRAM+4](23:0), {psr, pc}
←
A[DBRAM]
Logical shift to right; rd(15:0)
←
rd(15:0)>>rs(15:0), rd(23:16)
←
0, zero enters to MSB (
∗
1)
Logical shift to right; rd(15:0)
←
rd(15:0)>>imm7, rd(23:16)
←
0, zero enters to MSB (
∗
1)
Arithmetical shift to right; rd(15:0)
←
rd(15:0)>>rs(15:0), rd(23:16)
←
0, sign copied to MSB (
∗
1)
Arithmetical shift to right; rd(15:0)
←
rd(15:0)>>imm7, rd(23:16)
←
0, sign copied to MSB (
∗
1)
Logical shift to left; rd(15:0)
←
rd(15:0)<<rs(15:0), rd(23:16)
←
0, zero enters to LSB (
∗
1)
Logical shift to left; rd(15:0)
←
rd(15:0)<<imm7, rd(23:16)
←
0, zero enters to LSB (
∗
1)
rd(15:8)
←
rs(7:0), rd(7:0)
←
rs(15:8), rd(23:16)
←
0
D
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IL
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↔
↔
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↔
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IE
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0
0
↔
0
↔
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Z
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↔
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↔
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↔
↔
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N
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↔
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↔
↔
↔
↔
↔
↔
↔
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C
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↔
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↔
↔
↔
↔
↔
↔
↔
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V
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↔
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Mnemonic
Classification
Branch
Shift and swap
Flags
Instruction List (9) Assembly Programming
Remarks
∗
1) Number of bits to be shifted: Zero to three bits when rs/imm7 = 0–3, four bits when rs/imm7 = 4–7, eight bits when rs/imm7
≥
8