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EDR-5000
IM02602007E
Name
Description
Logic.LE66.Out
Signal: Latched Output (Q)
Logic.LE66.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE67.Gate Out
Signal: Output of the logic gate
Logic.LE67.Timer Out
Signal: Timer Output
Logic.LE67.Out
Signal: Latched Output (Q)
Logic.LE67.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE68.Gate Out
Signal: Output of the logic gate
Logic.LE68.Timer Out
Signal: Timer Output
Logic.LE68.Out
Signal: Latched Output (Q)
Logic.LE68.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE69.Gate Out
Signal: Output of the logic gate
Logic.LE69.Timer Out
Signal: Timer Output
Logic.LE69.Out
Signal: Latched Output (Q)
Logic.LE69.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE70.Gate Out
Signal: Output of the logic gate
Logic.LE70.Timer Out
Signal: Timer Output
Logic.LE70.Out
Signal: Latched Output (Q)
Logic.LE70.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE71.Gate Out
Signal: Output of the logic gate
Logic.LE71.Timer Out
Signal: Timer Output
Logic.LE71.Out
Signal: Latched Output (Q)
Logic.LE71.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE72.Gate Out
Signal: Output of the logic gate
Logic.LE72.Timer Out
Signal: Timer Output
Logic.LE72.Out
Signal: Latched Output (Q)
Logic.LE72.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE73.Gate Out
Signal: Output of the logic gate
Logic.LE73.Timer Out
Signal: Timer Output
Logic.LE73.Out
Signal: Latched Output (Q)
Logic.LE73.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE74.Gate Out
Signal: Output of the logic gate
Logic.LE74.Timer Out
Signal: Timer Output
Logic.LE74.Out
Signal: Latched Output (Q)
Logic.LE74.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE75.Gate Out
Signal: Output of the logic gate
Logic.LE75.Timer Out
Signal: Timer Output
Logic.LE75.Out
Signal: Latched Output (Q)
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