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EDR-5000
IM02602007E
Logic.LE71.Out
Signal: Latched Output (Q)
Logic.LE71.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE72.Gate Out
Signal: Output of the logic gate
Logic.LE72.Timer Out
Signal: Timer Output
Logic.LE72.Out
Signal: Latched Output (Q)
Logic.LE72.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE73.Gate Out
Signal: Output of the logic gate
Logic.LE73.Timer Out
Signal: Timer Output
Logic.LE73.Out
Signal: Latched Output (Q)
Logic.LE73.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE74.Gate Out
Signal: Output of the logic gate
Logic.LE74.Timer Out
Signal: Timer Output
Logic.LE74.Out
Signal: Latched Output (Q)
Logic.LE74.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE75.Gate Out
Signal: Output of the logic gate
Logic.LE75.Timer Out
Signal: Timer Output
Logic.LE75.Out
Signal: Latched Output (Q)
Logic.LE75.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE76.Gate Out
Signal: Output of the logic gate
Logic.LE76.Timer Out
Signal: Timer Output
Logic.LE76.Out
Signal: Latched Output (Q)
Logic.LE76.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE77.Gate Out
Signal: Output of the logic gate
Logic.LE77.Timer Out
Signal: Timer Output
Logic.LE77.Out
Signal: Latched Output (Q)
Logic.LE77.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE78.Gate Out
Signal: Output of the logic gate
Logic.LE78.Timer Out
Signal: Timer Output
Logic.LE78.Out
Signal: Latched Output (Q)
Logic.LE78.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE79.Gate Out
Signal: Output of the logic gate
Logic.LE79.Timer Out
Signal: Timer Output
Logic.LE79.Out
Signal: Latched Output (Q)
Logic.LE79.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE80.Gate Out
Signal: Output of the logic gate
Logic.LE80.Timer Out
Signal: Timer Output
Logic.LE80.Out
Signal: Latched Output (Q)
Logic.LE80.Out inverted
Signal: Negated Latched Output (Q NOT)
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