![background image](http://html1.mh-extra.com/html/eaton/edr-5000/edr-5000_nstallation-operation-and-maintenance-manual_3977585823.webp)
EDR-5000
IM02602007E
Name
Description
DI-8 X6.DI 8
Signal: Digital Input
Logic.LE1.Gate Out
Signal: Output of the logic gate
Logic.LE1.Timer Out
Signal: Timer Output
Logic.LE1.Out
Signal: Latched Output (Q)
Logic.LE1.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate Out
Signal: Output of the logic gate
Logic.LE2.Timer Out
Signal: Timer Output
Logic.LE2.Out
Signal: Latched Output (Q)
Logic.LE2.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate Out
Signal: Output of the logic gate
Logic.LE3.Timer Out
Signal: Timer Output
Logic.LE3.Out
Signal: Latched Output (Q)
Logic.LE3.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE4.Gate Out
Signal: Output of the logic gate
Logic.LE4.Timer Out
Signal: Timer Output
Logic.LE4.Out
Signal: Latched Output (Q)
Logic.LE4.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE5.Gate Out
Signal: Output of the logic gate
Logic.LE5.Timer Out
Signal: Timer Output
Logic.LE5.Out
Signal: Latched Output (Q)
Logic.LE5.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE6.Gate Out
Signal: Output of the logic gate
Logic.LE6.Timer Out
Signal: Timer Output
Logic.LE6.Out
Signal: Latched Output (Q)
Logic.LE6.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE7.Gate Out
Signal: Output of the logic gate
Logic.LE7.Timer Out
Signal: Timer Output
Logic.LE7.Out
Signal: Latched Output (Q)
Logic.LE7.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE8.Gate Out
Signal: Output of the logic gate
Logic.LE8.Timer Out
Signal: Timer Output
Logic.LE8.Out
Signal: Latched Output (Q)
Logic.LE8.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE9.Gate Out
Signal: Output of the logic gate
Logic.LE9.Timer Out
Signal: Timer Output
Logic.LE9.Out
Signal: Latched Output (Q)
Logic.LE9.Out inverted
Signal: Negated Latched Output (Q NOT)
www.eaton.com
823