Xtium2-CL MX4 User's Manual
Declarations of Conformity
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97
Status LED Functional Description
S Boot-up/PCIe status LED
Color
State
Description
Red
Solid
FPGA firmware not loaded
Green
Solid
Normal FPGA firmware loaded, Gen3 speed, link width x4
Green
Flashing
Normal FPGA firmware loaded, Gen1/Gen2 speed, link width x4
Solid
Normal FPGA firmware loaded, Gen3 speed, link width not x4
Flashing
Normal FPGA firmware loaded, Gen1/Gen2 speed, link width not x4
Blue
Solid
Safe FPGA firmware loaded, Gen3 speed
Blue
Flashing
Safe FPGA firmware loaded, Gen1/Gen2 speed
Red
Flashing
PCIe Training Issue
–
Board will not be detected by computer
Camera Link LEDs
(L1 = Camera Link connector #1, L2 = Camera Link connector #2)
Color
State
Description
Red
Solid
No Camera Link pixel clock detected
Green
Solid
Camera Link pixel clock detected. No line valid detected.
Note: for L2, when configuring for Full Camera Link, both pixel clock on
the 2
nd
cable must be detected.
Green
Slow Flashing
~1 Hz
Camera Link pixel clock and line valid signal detected
Note: for L2, when configuring for Full Camera Link, both line valid on
the 2
nd
cable must be detected.
Green
Fast Flashing
~8 Hz
Acquisition in progress
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Notes 1: When using a Full configuration, if the input on CL-1 is configured as Camera Link
Base, the L2 (for CL-2) will remain RED at all times.
▪
Note 2: LEDs L1 and L2 are independent.
▪
Note 3: Full FPGA defaults to Camera Link Medium configuration.
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Note 4: For a Pixel Clock and Line Valid to be detected, the following rules apply:
•
CL-1: Requires 1 clock and 1 LVAL
•
CL-2: Camera Link Base configuration: N/A
•
CL-2: Camera Link Medium configuration requires 1 clock and 1 LVAL
•
CL-2: Camera Link Full/80-bit configurations requires 2 clocks and 2 LVAL