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Xtium2-CL MX4 Reference
Xtium2-CL MX4 User's Manual
Acquisition Timing
PCLK
2
LVAL
3
FVAL
(Vsync)
Pixel Clock Range: 20 MHz up to 85 MHz
Min/Max
9
HB
5
Min/Max
4,9
VB
6
LVAL/FVAL setup time
1
: Minimum 15ns
DATA
first
7
last
8
(Hsync)
Figure 17: Acquisition Timing
▪
1
The setup times for LVAL and FVAL are the same. Both must be high and stable before the rising
edge of the Pixel Clock.
▪
2
Pixel Clock must always be present
▪
3
LVAL must be active high to acquire camera data
▪
4
Minimum of 1
▪
5
HB - Horizontal Blanking:
Minimum: 1 clock cycle
Maximum: no limits
▪
6
VB - Vertical Blanking:
Minimum: 1 line
Maximum: no limits
▪
7
First Active Pixel (unless otherwise specified in the CCA file
–
"Horizontal Back invalid = x" where ‘x’
defines the number of pixels to be skipped).
▪
▪
8
Last Active Pixel
–
defined in the CCA file
under “
Horizontal active = y"
–
where ‘y’ is the total
number of active pixels per tap.
▪
9
Maximum Valid Data:
▪
8-bits/pixel x 64k Pixels/line (LVAL)
▪
16-bits/pixel x 32k Pixels/line (LVAL)
▪
32-bits/pixel x 16k Pixels/line (LVAL)
▪
16 Million lines (FVAL)