Cypress PSoC CY8C23533, Техническое справочное руководство

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34 Document # 001-20559 Rev. *D
Section B: PSoC Core
INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page
19
)
1,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0] W : 00
EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page
23
)
x,FEh CPU_SC
R1 IRESS SLIMO ECO EXW ECO EX IRAMDIS # : 00
1,E0h OSC_CR
0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00
1,EBh ECO_TR PSSDC[1:0] W : 00
PHASE-LOCKED LOOP (PLL) REGISTERS (page
27
)
1,E0h OSC_CR
0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00
1,E2h
OSC_CR
2
PLLGAIN EXTCLKEN RSVD
SYSCLKX2
DIS
RW : 00
SLEEP AND WATCHDOG REGISTERS (page
33
)
0,E0h INT_MSK
0 VC3 Sleep GPIO Analog 1 Analog 0 V Monitor RW : 00
0,E3h RES_WD
T WDSL_Clear[7:0] W : 00
x,FEh CPU_SC
R1 IRESS SLIMO ECO EXW ECO EX IRAMDIS # : 00
x,FFh CPU_SC
R0 GIES WDRS PORS Sleep STOP # : XX
1,E0h OSC_CR
0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00
1,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0] W : 00
1,EBh ECO_TR PSSDC[1:0] W : 00
LEGEND
L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register.
# Access is bit specific. Refer to the
Register Details chapter on page 47
for additional information.
X The value for power on reset is unknown.
x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used.
C Clearable register or bit(s).
R Read register or bit(s).
W Write register or bit(s).
Summary Table of the Core Registers (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access