Cypress PSoC CY8C23533, Техническое справочное руководство

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Document # 001-20559 Rev. *D 183
Digital Blocks
17.1.10 SPI Protocol Function
The Serial Peripheral Interface (SPI) is a Motorola™ specification for implementing full-duplex synchronous serial communi-
cation between devices. The 3-wire
protocol uses both edges of the clock to enable synchronous communication, without
the need for stringent set up and hold requirements. Figure 17-5 shows the basic signals in a simple connection.
Figure 17-5. Basic SPI Configuration
A device can be a master or slave. A master outputs clock
and data to the
slave device and inputs slave data. A slave
device inputs clock and data from the master device and
outputs data for input to the master. The master and slave
together are essentially a circular shift register, where the
master generates the clocking and initiates data transfers.
A basic data transfer occurs when the master sends 8 bits of
data, along with eight clocks. In any transfer, both master
and slave transmit and receive simultaneously. If the master
only sends data, the received data from the slave is ignored.
If the master wishes to receive data from the slave, the mas-
ter must send dummy bytes to generate the clocking for the
slave to send data back.
17.1.10.1 SPI Protocol Signal Definitions
The SPI protocol signal definitions are located in Table 17-3 .
The use of the SS_ signal varies according to the capability
of the slave device.
17.1.11 SPI Master Function
The SPI Master (SPIM) offers SPI operating modes 0-3. By
default, the MSb of the data byte is shifted out first. An addi-
tional option can be set to reverse the direction and shift the
data byte out LSb first. (Refer to the timing diagrams for this
function on page
203 .)
When configured for SPIM, DR0 functions as a shift register,
with input from the DATA input (MISO) and output to the pri-
mary output F1 (MOSI). DR1 is the TX Buffer register and
DR2 is the RX Buffer register.
The SPI protocol requires data to be registered at the device
input, on the opposite edge of the clock that operates the
output shifter. An additional register (RXD), at the input to
the DR0 shift register, has been implemented for this pur-
pose. This register stores received data for one-half cycle,
before it is clocked into the shift register.
The SPIM controls data transmission between master and
slave, because it generates the bit clock for internal clocking
and for clocking the SPIS. The bit clock is derived from the
CLK input selection. Since the PSoC system clock genera-
tors produce clocks with varying duty cycles, the SPIM
divides the input CLK by two to produce a bit clock with a 50
percent duty cycle. This clock is gated, to provide the SCLK
output on the auxiliary output, during byte transmissions.
There are 4 control bits and 4 status bits in the control regis-
ter that provide for PSoC device interfacing and synchroni-
zation.
The SPIM hardware has no support for driving the Slave
Select (SS_) signal. The behavior and use of this signal is
application and PSoC-device dependent and, if required,
must be implemented in firmware.
SPI Master SPI Slave
MOSI
SCLK
SS_
MISO
MOSI
MISO
SCLK
Data is output by both
the Master and Slave, on
one edge of the clock.
Data is registered at the input
of both devices, on the
opposite edge of the clock.
MOSI
SCLK
SS_
MISO
Table 17-3. SPI Protocol Signal Definitions
Name Function Description
MOSI Master Out
Slave In Master data output.
MISO Master In Slave
Out Slave data output.
SCLK Serial Clock Clock generated by the master.
SS_ Slave Select
(active low) This signal is provided to enable multi-slave
connections to the MISO pin. The MOSI and
SCLK pins can be connected to multiple
slaves, and the SS_ input selects which slave
receives the input data and drives the MISO
line.