Cypress PSoC CY8C23533, Техническое справочное руководство

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Document # 001-20559 Rev. *D 171
16. Row Digital Interconnect (RDI)
This chapter explains the Row Digital Interconnect (RDI) and its associated registers. This chapter discusses a single digital
PSoC block row. It does not discuss the functions, inputs, or outputs for individual digital PSoC blocks. Therefore, the informa-
tion contained here is valid for 1 row configurations. Information about individual digital PSoC blocks is covered in the
Digital
Blocks chapter on page 177 . For a complete table of the RDI registers, refer to the “Summary Table of the Digital Registers”
on page 162 . For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 47 .
16.1 Architectural Description
Many signals pass through the digital PSoC block row on
their way to or from individual
digital blocks . However, only
a small number of signals pass though configurable circuits
on their way to and from digital blocks. The configurable cir-
cuits allow for greater flexibility in the connections between
digital blocks and global buses. What follows is a discussion
of the signals that are configurable by way of the registers
listed in the
“Register Definitions” on page 173 .
In Figure 16-1 , within a digital PSoC block row, there are
four digital PSoC Blocks. The first two blocks are of the type
basic (DBB).
The second two are of the type communication (DCB). This
figure shows the connections between digital blocks within a
row. Only the signals that pass outside the gray background
box in
Figure 16-1 are shown at the next level of hierarchy in
Figure 16-2 on page 172 .
In Figure 16-2 , the detailed view shown in Figure 16-1 of the
four PSoC block grouping, has been replaced by the box in
the center of the figure labeled “4 PSoC Block Grouping.”
The rest of the configurable nature of the Row Inputs (RI),
Row Outputs (RO), and Broadcast clock net (BC) is shown
for the next level of hierarchy.
Figure 16-1. Detailed View of Four PSoC Block Grouping
CLKS[15:0]
DATAS[15:0]
Chaining Signals
Digital PSoC
Block 0
Basic
DB[7:0]
Inputs
INT
RO[3:0]
AUXDATA[3:0]
To next block
From next block
From previous block
To previous block
Bus Interface
Input Signals
Output Signals
Broadcast
DB[7:0]
DBI
TPB
FPB
AUX[3:0]
DATA[15:0]
CLK[15:0]
TNB
FNB
RO[3:0
INT[3:0
BC
CLKS[15:0]
DATAS[15:0]
Chaining Signals
Digital PSoC
Block 1
Basic
DB[7:0]
Inputs
INT
RO[3:0]
AUXDATA[3:0]
To next block
From next block
From previous block
To previous block
Bus Interface
Input Signals
Output Signals
Broadcast
CLKS[15:0]
DATAS[15:0]
Chaining Signals
DB[7:0]
Inputs
INT
RO[3:0]
AUXDATA[3:0]
To next block
From next block
From previous block
To previous block
Bus Interface
Input Signals
Output Signals
Broadcast
CLKS[15:0]
DATAS[15:0]
Chaining Signals
Digital PSoC
Block 3
Communications
DB[7:0]
Inputs
INT
RO[3:0]
AUXDATA[3:0]
To next block
From next block
From previous block
To previous block
Bus Interface
Input Signals
Output Signals
Broadcast
Digital PSoC
Block 2
Communications