Document # 001-20559 Rev. *D
111
0,E7h
13.2.59
DEC_CR1
Decimator Control Register 1
This register is used to configure signals for ADC operation.
Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always
be written with a value of ‘0’. For additional information, refer to the
“Register Definitions” on page 293
in the Decimator chap-
ter.
7
ECNT
0
Disable decimator as a counter for incremental ADC. Configure for delta sigma operation.
1
Enable decimator as a counter for incremental ADC operation.
6
IDEC
Invert the Digital Block Latch Control (selected by DCLKS3, DCLKS2, DCLKS1, and DCLKS0).
0
Non-inverted
1
Inverted
5:3
ICLKSx
Incremental/SSADC Gate Source. Along with ICLKS0 in DEC_CR0, selects any one of the digital
blocks in your device. The bit value for a digital block number that does not exist in a specific PSoC
should be considered reserved. For example, a PSoC device with 2 rows may choose any block num-
bered 0x or 1x, but not a block numbered 2x or 3x.
(5:3
ICLKSx
ICLKS3, ICLKS2, ICLKS1
(cont.)
000b
Digital block 02
001b
Digital block 12
010b
Digital block 01
011b
Digital block 11
100b
Digital block 00
101b
Digital block 10
110b
Digital block 03
111b
Digital block 13
2:0 DCLKSx
Decimator Latch Select. Along with DCLKS0 in DEC_CR0, selects any one of the digital blocks in
your device. The bit value for a digital block number that does not exist in a specific PSoC should be
considered reserved. For example, a PSoC device with 2 rows may choose any block numbered 0x
or 1x, but not a block numbered 2x or 3x.
DCLKS3, DCLKS2, DCLKS1
000b
Digital block 02
001b
Digital block 12
010b
Digital block 01
011b
Digital block 11
100b
Digital block 00
101b
Digital block 10
110b
Digital block 03
111b
Digital block 13
Individual Register Names and Addresses:
0,E7h
DEC_CR1: 0,E7h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
ECNT
IDEC
ICLKS3
ICLKS2
ICLKS1
DCLKS3
DCLKS2
DCLKS1
Bits
Name
Description
Содержание PSoC CY8C23533
Страница 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Страница 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Страница 24: ...24 Document 001 20559 Rev D Section A Overview ...
Страница 30: ...30 Document 001 20559 Rev D Pin Information ...
Страница 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Страница 60: ...60 Document 001 20559 Rev D RAM Paging ...
Страница 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Страница 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Страница 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Страница 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Страница 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Страница 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Страница 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Страница 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Страница 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Страница 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Страница 296: ...232 Document 001 20559 Rev D Analog Interface ...
Страница 304: ...240 Document 001 20559 Rev D Analog Array ...
Страница 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Страница 312: ...248 Document 001 20559 Rev D Analog Reference ...
Страница 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Страница 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Страница 374: ...310 Document 001 20559 Rev D I2C ...
Страница 400: ...336 Document 001 20559 Rev D Section G Glossary ...