Comtech EF Data SDM-9000, Инструкция по установке и эксплуатации

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SDM-9000 Satellite Modem Theory of Operation
Rev.4 5–13
5.3.3 Theory of Operation
The demodulator functions as an advanced digital coherent phase-lock receiver and
Viterbi decoder. The demodulator is intended to operate at data rates greater than
10 Mbit/s, and complies with the IESS-308 specifications for IDR carriers greater than
10 Mbit/s.
The demodulator provides the following functions:
•
Analog-to-Digital (A/D) conversion of analog baseband data using Automatic
Gain/Offset Control (AGC, AOC)
•
Mapping I and Q values to eight-level soft-decision values
•
Commutation of code words to three parallel decoders per IESS-308
specifications for IDR carriers greater than 10 Mbit/s
•
Symbol clock to data clock rate exchange and depuncturing (null symbol
insertion) logic
•
Phase and puncture pattern ambiguity resolution
•
Three parallel Viterbi decoders
•
Three parallel differential decoders
•
A DDS-based digital clock recovery PLL
•
A DDS-based digital carrier recovery PLL (Costas Loop)
•
Local microprocessor based M&C circuitry for control of all aspects of the
demodulator operation, as well as performance and fault reporting to the host
M&C
The 50 to 180 MHz modulated IF signal enters the RF Module for conversion to In-phase
(I) and Quadrature (Q) analog baseband channels. The I and Q channels are then passed
to the Nyquist filter daughter board, where I and Q are filtered through identical analog
Nyquist filters. The output of the Nyquist filters is passed back down to the demodulator
board through the offset amplifiers and A/D converters. Optionally, the output of the
I channel A/D can be delayed by half a symbol period for Offset QPSK operation
(OQPSK). The digitized I and Q data is a filtered, digital representation of the received
signal.