Broadcom BCM1125, Руководство пользователя

Страница: 131 / 516

User Manual BCM1250/BCM1125/BCM1125H
10/21/02
B r o a d c o m C o r p o r a t i o n
Document 1250_1125-UM100CB-R Section 6: DRAM Page 103
S e c t i o n 6 : D R A M
I
NTRODUCTION
The part incorporates a DDR SDRAM controller that works closely with the level 2 cache to provide a high
performance memory system. The BCM1250 memory controller includes two channels each providing a 64 bit
data path with 8 bit ECC. The BCM1125/H parts have a memory controller with a single channel providing a
64 bit data path with 8 bit ECC. Each channel can directly support up to two standard two physical bank JEDEC
184 pin DDR DIMMs (for a total of four DIMMs on a BCM1250) running at 133MHz clock (266MHz data rate,
sometimes called PC2100 DIMMs based on PC266A parts) and allows for performance to increase as the
DIMMs support higher data rates. In a more controlled electrical environment, with the DRAMs mounted on
the main board and traces tightly controlled the memory controller can run up to 200MHz clock giving a
400MHz data rate. The peak memory bandwidth for a single channel using standard (133 MHz clock) DIMMs
is 16 Gbit/s and increases up to 50 Gbit/s for a high speed (200 MHz clock) design using both channels.
The memory controller supports three types of memory all of which use SSTL_2 signalling levels and the
conventional multiplexed address bus.
• Standard DDR SDRAM which may be mounted on board or on DIMMs.
• Standard DDR SGRAM which can be on DIMMs but are designed to be mounted on the main board and
run with faster cycle times than standard DDR. The memory controller does not make use of any of the
graphics features.
• Fujitsu/Toshiba/Samsung DDR FCRAM (Fast Cycle RAM) which is designed to be mounted on the
main board. These parts have smaller rows and a much simplified command set allowing them to have
both faster cycle times and lower access latency than standard DDR.
Each channel can support up to 1 GByte of memory using 256 Mbit technology parts. As larger DRAMs
become available this will increase to 2 GByte with 512 Mbit parts and 4 GByte with 1 Gbit parts (note that
gigabit parts that use 14 row address bits are only supported on the BCM1125/H and versions of the BCM1250
supporting PERIPH_REV3 or later). A special large memory mode allows these sizes to be doubled, but
requires the use of an external decoder and may be lower performance.
A C
OMMENT ON THE TERM
B
ANK
The term "Bank" is unfortunately used in a couple of different ways when discussing DDR SDRAM memory
systems.
The first use of bank is to describe the organization within a memory device, most devices have four internal
banks and thus need two bank address bits (BA[1:0]). The number of banks on a device sets the number of
pages that it can have open at a given time.
The second use of bank is to describe the physical groups of devices that are enabled by a single chip select.
Standard DDR 184 pin DIMMs can have two physical banks and thus need two chip selects. Each physical
bank corresponds to one load on the data and DQS signal lines. The number of loads on the address lines for
a physical bank depends on the organization of the memory devices. For the 64 bit wide data path used by the
memory channel using x8 devices gives 8 address loads per physical bank (9 if ECC is used). Using x16
devices gives 4 (or 5) loads and using x32 devices gives 2 (or 3) loads.
In this chapter the unqualified term bank will only be used to refer to internal banks. Physical banks will always
be described as such.