Quad OC12 Network Access Module
Plexus 9000 Planning and Engineering Guide
Issue 2, May 28, 2004
Section 130-120-750
5-180
Telica,
Inc.
The incoming optical signal is converted to electrical signals and they are
passed to the clock recovery units (CRUs). The CRUs extract a clock
from the data stream. This clock is then passed to both the framer and a
clock circuit. The four recovered clocks, one from each CRU, are used to
loop-time the ANA by allowing the system to be connected into the
transmit phased-locked-loop.
The outgoing data is passed from the framer directly to the optical
transceivers (Optical Data Links) which convert the electrical signals to
light energy (i.e., an optical signal).
The framer provides complete encapsulation and de-encapsulation for
packet and ATM streams into and out of SONET/SDH payloads.
5.16.3.2
ATM Port Controllers (APCs)
The APCs maintain and manage the ATM Virtual Connections. They
perform the scheduling and policing of ATM functions on the data
flowing through the module.
5.16.3.3 PHAZITs
This circuitry links the Serializer/Deserializer (SERDES) devices to the
APCs. The Phazits are a 4:2 MUX, which switch the active switch fabric
ports to the APCs, synchronizes transfers between the SERDES and the
APCs and checks the integrity of the data from the midplane.
5.16.3.4 Serializer/Deserializer
(SERDES)
The SERDES takes the 1.0GHz embedded clock/data stream from the SF
and extracts a clock from it and provides 8-bit-wide data to the Phazit
circuitry or takes the 8-bit-wide data from the Phazit and embeds the clock
and sends the clock/data stream to the SF module.
5.16.3.5 NACSTER
The NACSTER implements the maintenance link functionality of the
MLBA (Maintenance Link Bus Adapter), which provides a serialized
point-to-point interconnect between the SF module and each Network
Access module and its microprocessor. This link is used to reset a
module, detect CLEI code, control the LEDs located on the module,
download images to the processor’s memory, program the circuit switch
registers and communicate operational status to the SP. It also provides a
bridge between the PCI bus and the non-PCI-bus-based peripherals, such
as the Framer and the APC devices.
