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Plexus 9000 Planning and Engineering Guide
Rear System Processor Timing Module
Section 130-120-250
Issue 2, April 23, 2004
Telica, Inc.
5-69
5.5.3 Theory
of
Operation
provides a simplified block diagram of the rear SP, which is
described in the following paragraphs.
P172-AA
03-15-02
MIDPLANE
Connectors
Disk Drive
IDE Bus
USB Port 0
USB Port 1
Serial Debug
Port A
Serial Debug
Port B
DB-9
DB-9
USB
Connector
USB
Connector
USB0
USB1
RS232-Port A
RS232-Port B
PCI Bus
Management
Controller
Signaling
Controller
RJ45
Management
Ethernet
DS1 Monitor
and Test Port
Bantam
Jacks
Monitor Port
Test Port
RJ45
Signaling
Ethernet
Replication
Controller
Figure 5.5-2. SP/TMG Rear Module Block Diagram
5.5.3.1 Power
The rear SP/TMG module receives its local voltages (5Vdc, 3Vdc, etc.)
from the front SP/TMG’s DC-to-DC converter, which converts the -48
volts supplied from the backplane.