
Rear System Processor Timing Module
Plexus 9000 Planning and Engineering Guide
Issue 2, April 23, 2004
Section 130-120-250
Telica, Inc.
5-68
Table 5.5-A. Craft Connector
Name Pin
Description
1 DCD
2 RXD
3 TXD
4 DTR
5 GND
6 DSR
7 RTS
8 CTS
P218-AA
07-07-00
1
5
9
6
9 RI
Table 5.5-B. Ethernet Connector
Name Pin
Description
1 TX+
2 TX-
3 RX+
4
5
6 RX-
7
P217-AA
07-07-00
1
2
3
4
5
6
7
8
8
Table 5.5-C. DS1 Test Jacks, J7, J8, J9 AND J10
Name Dir.
Pin
Description
1 S1
2 RN1
3 TN1
4 R1
In
5 T1
1 S2
2 RN2
3 TN2
4 R2
DS1 TEST
P219-AA
06-06-00
R
IN
IN
OUT
T
T
OUT
R
Out
5 T2
Note:
The IN jack, J9, is not used.
72
P122-AA
07-07-00
REAR
CARD
SYSTEM
PROCESSOR
TIMING
USB 1
J1
USB 2
J2
J3
CRAFT
J4
COM
S
I
G
E
N
E
T
O
S
E
N
E
T
J5
J6
J7
I
J8
O
I
O
J9
J10
DS1 TEST