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Front Dual System Processor Timing Module 2
Plexus 9000 Planning and Engineering Guide
Issue 1, April 23, 2004
Section 130-120-210
5-44
Telica,
Inc.
5.3.3 Theory
of
Operation
provides a simplified block diagram of the Dual SP. The SP
consists of the Timing (TMG) section and the processor section, which are
described in the following paragraphs.
CLOCK
GENERATION
CIRCUITRY
BUFFERS
Test Monitor
TDM BUS
Craft
DB-9
QUAD
T1
FRAMER/LIU
MLBA
TIMING
BITS A
BITS B
Monitor
Test
Clock
To Rear
System
Processor
From Rear
Switch
Fabric
MID PLANE
Craft
ENET
STRAT 3
P484-AA
03-18-02
SRAM
Flash
SDRAM
Serial
Interface
Ethernet
Processor
Bus
Controller
SRAM
Flash
SDRAM
Serial
Interface
Processor
Bus
Controller
BRIDGE
Ethernet
Ethernet
Switch
Ethernet
Debug
Port
SAR
Figure 5.3-2. Block Diagram of Dual System Processor and Module
5.3.3.1 Power
The front SP module has its own DC-to-DC converter (not shown in
), which converts the -48 volts supplied from the backplane to
the local voltages required (5V, 3V, etc.) for the module. The front
module also supplies these voltages for the rear SP/TMG module.