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Plexus 9000 Planning and Engineering Guide
DS1 I/O Front Module
Section 130-120-400
Issue 4, April 23, 2004
Telica, Inc.
5-115
5.9.3 Theory
of
Operation
Each DS-1 IOM has 28 DS1 ports that are controlled by a microprocessor.
In the transmit direction the DS-1s enter the seven QFALCs (Quad Framer
And Line Interface Components) where they are multiplexed together to a
signal which passes to the TSU (To Switch Unit) circuitry. In the TSU the
signals are converted to ATM cells that are sent to the Parallel In/Serial
Out Interface where they are converted from parallel to serial. The serial
data is sent to the SF module for switching.
In the receive direction the serial data from the SF module is received at
the Serial In/Parallel Out interface to be converted to parallel data for the
FSU (From Switch Unit) circuitry. The FSU converts the ATM cells back
to a 4 DS-1 signal for the QFALCs that demultiplex them back to DS-1s
for the mid-plane and the rear module. Refer to
for a block
diagram of the IOM.
To
Rear
Card
To/From
System
Processor/
Switch
Fabric
To
Switch
Fabric
IOM
Clocks
From
Switch
Fabric
MID PLANE
DS1-IOM front
Clock
Control
MLBA
TSU
RAM
RAM
FSU
QFALC
SAR
XCVR/Buffers
Bus Converter
Parallel
serial
Interface
P220-AA
08-14-00
Processor
Memory
Figure 5.9-2. DS-1 IOM Block Diagram