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Front Dual System Processor Timing Module 2
Plexus 9000 Planning and Engineering Guide
Issue 1, April 23, 2004
Section 130-120-210
5-40
Telica,
Inc.
the secondary, and generating alarms when failures on the input clock
lines occur.
The Plexus 9000 provides complete timing system redundancy for
protection against either BITS source or internal clock failure. Holdover
is provided in the event of a complete loss of external BITS timing.
The system processor section with memory provides the processing for the
Plexus 9000. It includes a FAM for processing all system events, an
EQM, which keeps track of state information, a TL1 Agent that handles
TL1 commands and a System Fault Manager that is responsible for state
changes.
The front panel of the SP front module has two craft interfaces:
•
An RS-232 serial craft interface operating at a fixed 9600 baud
•
A 10/100Base-T Ethernet craft interface.
5.3.2.1 Limitations
The functions of SP are limited by the revision of SF module and the
Midplane. Refer to
Table 5.3-A. Dual System Processor (89-0389) and Switch Fabric
Modules
Dual SP
SW/FAB
Midplane
Functions and Limitations
I
DS-1 and Triple DS-3 IOMs,
more processing power but no
access to second processor
Rev. B
II/III
DS-1, Triple and Octal DS-3
IOMs, more processing power
but no access to second
processor
I
DS-1 and Triple DS-3 IOMs,
more processing power but no
access to second processor
Rev. A/B
Rev. C/D
II/III
DS-1, Triple and Octal DS-3
IOMS, full access to second
processor and memory for more
processing power
Notes:
1
. Chassis 85-3000 has Midplane I, Chassis 85-3004 has
Midplane II, and Chassis 85-3007 and 85-3008 have
Midplane III.
2.
Single and Dual refer to the processors on the System
Processor module, not the number of processors in the
system.