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Plexus 9000 Planning and Engineering Guide
Triple DS3/STS-1 I/O Front Module
Section 130-120-500
Issue 2, March 26, 2004
Telica, Inc.
5-137
5.11.3 Theory
of
Operation
Each Triple DS-3 IOM or Triple DS-3/STS-1 IOM has 3 DS-3 or STS-1
interfaces that are controlled by a microprocessor. In the transmit
direction the DS-3s or STS-1s enter the interfaces from the rear module.
Each interface demultiplexes the DS-3 or STS-1 into 28 DS-1s that pass to
the TSU circuitry. In the TSU, the signals are converted to ATM cells that
are sent to the Parallel In/Serial Out Interface where they are converted
from parallel to serial. The serial data is sent to the SF module for
switching.
The 89-0410 and 89-0424 IOMs have digital signal processor (DSP)
circuitry on a daughter card for use during DTMF digit collection.
In the receive direction the serial data from the SF module is received at
the Serial In/Parallel Out interface to be converted to parallel data for the
FSU circuitry. The FSU converts the ATM cells back to DS-1 signals for
the DS-3 or STS-1 interface that multiplexes them back to DS-3 or STS-1
for the midplane and the rear module.
See
for a block diagram of the IOM module.
To/From
Rear
Card
To/From
System
Processor/
Switch
Fabric
To/From
Switch
Fabric
MID PLANE
Clock
Control
PCI BRIDGE
MLBA
SAR
TSU
RAM
RAM
FSU
E
E
P
R
O
M
Parallel
serial
Interface
P487-AA
01-06-03
TRIPLE DS3 STS-1 IOM front
LIU/Super mapper
Processor
HDLC
LATCH
SDRAM
Memory
Connector
Buffers
FPGA
DSP
REG
L2
Cache
XCVR
FLASH
Memory
Figure 5.11-2. Triple DS-3/STS-1 IOM Block Diagram