AT91CAP9A-DK Development Kit User Guide
3-19
6321B–CAP–02-Jul-07
13
B2
IO
DIFFIO_TX30p
T28
FPGA182
14
B2
IO
DIFFIO_RX30n
P31
FPGA181
15
5VPCI
16
B2
IO
DIFFIO_TX30n
T27
FPGA183
18
B2
IO
DIFFIO_RX29p
R31
FPGA184
19
VCCIO2
22
B2
IO
DIFFIO_RX29n
R30
FPGA185
26
GND
27
VCCIO2
28
B2
IO
DIFFIO_TX29p
T23
FPGA186
29
B2
IO
DIFFIO_TX29n
T22
FPGA187
30
GND
31
GND
32
B2
CLK1n
INPUT
T29
FPGA190
34
VCCIO2
35
B2
IO
CLK0p/DIFFIO_RX_C0p
T32
FPGA189
36
B2
IO
CLK0n/DIFFIO_RX_C0n
T31
FPGA188
37
VCCIO2
38
B2
IO
DIFFIO_TX32n
R24
FPGA191
39
B3
IO
CLK14p
A17
FPGA192
40
GND
41
B3
IO
CLK14n
B17
FPGA193
42
B3
IO
CLK15p
C17
FPGA194
43
GND
44
B3
IO
CLK15n
D17
FPGA195
45
B3
IO
K18
FPGA196
46
VCCIO3
47
B3
IO
F18
FPGA197
48
B3
IO
F19
FPGA198
49
VCCIO3
50
B3
IO
E17
FPGA199
51
B3
IO
G20
FPGA200
52
GND
53
B3
IO
F20
FPGA201
54
B3
IO
DQS10T
D19
FPGA202
55
GND
Table 3-4. PCI64 Extension Connector Table (Continued)
J9 Pin
FPGA
Bank
FPGA Pin
Function
Other FPGA Pin Information
FPGA Ball
Board Net
Содержание AT91CAP9
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