7-78
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
B6
IO
DIFFIO_RX90n
W2
UGRID53
B6
IO
DIFFIO_RX90p
W1
UGRID54
B6
IO
DIFFIO_TX89n
U6
UGRID55
B6
IO
DIFFIO_TX89p
U5
UGRID56
B6
IO
DIFFIO_RX89n
V3
UGRID57
B6
IO
DIFFIO_RX89p
V2
UGRID58
B6
CLK9n
INPUT
U4
UGRID59
B8
IO
DEV_CLRn
AG19
UGRID6
B6
CLK9p
INPUT
U3
UGRID60
B6
IO
CLK8n/DIFFIO_RX_C2n
U2
UGRID61
B6
IO
CLK8p/DIFFIO_RX_C2p
U1
UGRID62
B9
IO
PLL5_FBn/OUT2n
E15
UGRID63
B9
IO
PLL5_FBp/OUT2p
D15
UGRID64
B9
IO
PLL5_OUT0n
C15
UGRID65
B9
IO
PLL5_OUT0p
B15
UGRID66
B9
IO
PLL5_OUT1n
D16
UGRID67
B9
IO
PLL5_OUT1p
C16
UGRID68
B11
IO
PLL11_OUT0p
B18
UGRID69
B8
IO
nCS
AG18
UGRID7
B11
IO
PLL11_OUT0n
C18
UGRID70
B11
IO
PLL11_OUT1p
D18
UGRID71
B11
IO
PLL11_OUT1n
E18
UGRID72
B11
IO
PLL11_FBp/OUT2p
A19
UGRID73
B11
IO
PLL11_FBn/OUT2n
B19
UGRID74
B3
IO
INIT_DONE
G25
UGRID75
B12
IO
PLL12_FBn/OUT2n
AL19
UGRID8
B12
IO
PLL12_FBp/OUT2p
AM19
UGRID9
B11
VCC_PLL11_OUT
J17
VCC_PLL11
B12
VCC_PLL12_OUT
AF16
VCC_PLL12
B9
VCC_PLL5_OUT
J16
VCC_PLL5
B10
VCC_PLL6_OUT
AF15
VCC_PLL6
VCCA_PLL6
AE15
VCCA_PLL
VCCA_PLL9
AE7
VCCA_PLL
VCCA_PLL12
AF18
VCCA_PLL
VCCA_PLL8
AF26
VCCA_PLL
VCCA_PLL5
G15
VCCA_PLL
Table 7-6. FPGA Pins Sorted by Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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