7-46
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
B6
IO
DIFFIO_TX96p
W4
UGRID28
B6
IO
DIFFIO_RX96n
AB4
UGRID29
B6
IO
DIFFIO_RX96p
AB3
UGRID30
B6
IO
DIFFIO_TX95n
W7
UGRID31
B6
IO
DIFFIO_TX95p
W6
UGRID32
B6
IO
DIFFIO_RX95n
AB2
UGRID33
B6
IO
DIFFIO_RX95p
AB1
UGRID34
B6
IO
DIFFIO_TX94n
W9
UGRID35
B6
IO
DIFFIO_TX94p
W8
UGRID36
B6
IO
DIFFIO_RX94n
Y5
UGRID37
B6
IO
DIFFIO_RX94p
Y4
UGRID38
B6
IO
DIFFIO_TX93n
V5
UGRID39
B6
IO
DIFFIO_TX93p
V4
UGRID40
B6
IO
DIFFIO_RX93n
AA4
UGRID41
B6
IO
DIFFIO_RX93p
AA3
UGRID42
B6
IO
DIFFIO_TX92n
V7
UGRID43
B6
IO
DIFFIO_TX92p
V6
UGRID44
B6
IO
DIFFIO_RX92n
AA2
UGRID45
B6
IO
DIFFIO_RX92p
AA1
UGRID46
B6
IO
DIFFIO_TX91n
V10
UGRID47
B6
IO
DIFFIO_TX91p
V9
UGRID48
B6
IO
DIFFIO_RX91n
Y3
UGRID49
B6
IO
DIFFIO_RX91p
Y2
UGRID50
B6
IO
DIFFIO_TX90n
U11
UGRID51
B6
IO
DIFFIO_TX90p
U10
UGRID52
B6
IO
DIFFIO_RX90n
W2
UGRID53
B6
IO
DIFFIO_RX90p
W1
UGRID54
B6
IO
DIFFIO_TX89n
U6
UGRID55
B6
IO
DIFFIO_TX89p
U5
UGRID56
B6
IO
DIFFIO_RX89n
V3
UGRID57
B6
IO
DIFFIO_RX89p
V2
UGRID58
B6
CLK9n
INPUT
U4
UGRID59
B6
CLK9p
INPUT
U3
UGRID60
B6
IO
CLK8n/DIFFIO_RX_C2n
U2
UGRID61
B6
IO
CLK8p/DIFFIO_RX_C2p
U1
UGRID62
B6
VREFB6N1
VREFB6N1
AD5
VREFB6
Table 7-5. FPGA Pins Sorted by Bank/Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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