7-76
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
B7
IO
DQ5B
AF10
SODIMM_D9
B7
IO
DQS0B
AK4
SODIMM_DQS0
B7
IO
DQS2B
AL5
SODIMM_DQS1
B6
IO
DIFFIO_TX102n
AA11
SODIMM_S0
B6
IO
DIFFIO_TX102p
AA10
SODIMM_S1
B6
IO
DIFFIO_RX100n
AE2
SODIMM_S10
B6
IO
DIFFIO_RX100p
AE1
SODIMM_S11
B6
IO
DIFFIO_TX99n
W11
SODIMM_S12
B6
IO
DIFFIO_TX99p
W10
SODIMM_S13
B6
IO
DIFFIO_RX99n
AD2
SODIMM_S14
B6
IO
DIFFIO_RX99p
AD1
SODIMM_S15
B6
IO
DIFFIO_TX98n
Y9
SODIMM_S16
B6
IO
DIFFIO_TX98p
Y8
SODIMM_S17
B6
IO
DIFFIO_RX98n
AC4
SODIMM_S18
B6
IO
DIFFIO_RX102n
AF2
SODIMM_S2
B6
IO
DIFFIO_RX102p
AF1
SODIMM_S3
B6
IO
DIFFIO_TX101n
Y11
SODIMM_S4
B6
IO
DIFFIO_TX101p
Y10
SODIMM_S5
B6
IO
DIFFIO_RX101n
AE4
SODIMM_S6
B6
IO
DIFFIO_RX101p
AE3
SODIMM_S7
B6
IO
DIFFIO_TX100n
AA7
SODIMM_S8
B6
IO
DIFFIO_TX100p
AA6
SODIMM_S9
B8
TRST
TRST
AK30
TRST
B8
IO
CS
AC22
UGRID0
B8
IO
CLKUSR
AD23
UGRID1
B12
IO
PLL12_OUT1n
AH18
UGRID10
B12
IO
PLL12_OUT1p
AJ18
UGRID11
B12
IO
PLL12_OUT0n
AK18
UGRID12
B12
IO
PLL12_OUT0p
AL18
UGRID13
B10
IO
PLL6_OUT1p
AJ15
UGRID14
B10
IO
PLL6_OUT1n
AH15
UGRID15
B10
IO
PLL6_OUT0p
AK16
UGRID16
B10
IO
PLL6_OUT0n
AJ16
UGRID17
B10
IO
PLL6_FBp/OUT2p
AL15
UGRID18
B10
IO
PLL6_FBn/OUT2n
AK15
UGRID19
B8
IO
nWS
AE23
UGRID2
Table 7-6. FPGA Pins Sorted by Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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