7-30
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
VCCIO8
AM30
VCCIO_8
B1
IO
CLK2p/DIFFIO_RX_C1p
U32
FPGA0
B1
IO
CLK2n/DIFFIO_RX_C1n
U31
FPGA1
B1
IO
DIFFIO_TX27p
U28
FPGA10
B1
IO
DIFFIO_TX27n
U27
FPGA11
B1
IO
DIFFIO_RX26p
AA32
FPGA12
B1
IO
DIFFIO_RX26n
AA31
FPGA13
B1
IO
DIFFIO_TX26p
V29
FPGA14
B1
IO
DIFFIO_TX26n
V28
FPGA15
B1
IO
DIFFIO_RX25p
Y31
FPGA16
B1
IO
DIFFIO_RX25n
Y30
FPGA17
B1
IO
DIFFIO_TX25p
V24
FPGA18
B1
IO
DIFFIO_TX25n
V23
FPGA19
B1
CLK3p
INPUT
U30
FPGA2
B1
IO
DIFFIO_RX24p
AB32
FPGA20
B1
IO
DIFFIO_RX24n
AB31
FPGA21
B1
IO
DIFFIO_TX24p
W29
FPGA22
B1
IO
DIFFIO_TX24n
W28
FPGA23
B1
IO
DIFFIO_RX23p
AA30
FPGA24
B1
IO
DIFFIO_RX23n
AA29
FPGA25
B1
IO
DIFFIO_TX23p
W27
FPGA26
B1
IO
DIFFIO_TX23n
W26
FPGA27
B1
IO
DIFFIO_RX22p
Y29
FPGA28
B1
IO
DIFFIO_RX22n
Y28
FPGA29
B1
CLK3n
INPUT
U29
FPGA3
B1
IO
DIFFIO_TX22p
W25
FPGA30
B1
IO
DIFFIO_TX22n
W24
FPGA31
B1
IO
DIFFIO_RX21p
AB30
FPGA32
B1
IO
DIFFIO_RX21n
AB29
FPGA33
B1
IO
DIFFIO_TX21p
Y27
FPGA34
B1
IO
DIFFIO_TX21n
Y26
FPGA35
B1
IO
DIFFIO_RX20p
AC32
FPGA36
B1
IO
DIFFIO_RX20n
AC31
FPGA37
B1
IO
DIFFIO_TX20p
AA27
FPGA38
B1
IO
DIFFIO_TX20n
AA26
FPGA39
B1
IO
DIFFIO_RX28p
V31
FPGA4
Table 7-5. FPGA Pins Sorted by Bank/Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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