AT91CAP9A-DK Development Kit User Guide
7-77
6321B–CAP–02-Jul-07
B6
FPLL9CLKp
INPUT
AJ3
UGRID20
B6
FPLL9CLKn
INPUT
AJ4
UGRID21
B6
IO
DIFFIO_RX98p
AC3
UGRID22
B6
IO
DIFFIO_TX97n
Y7
UGRID23
B6
IO
DIFFIO_TX97p
Y6
UGRID24
B6
IO
DIFFIO_RX97n
AC2
UGRID25
B6
IO
DIFFIO_RX97p
AC1
UGRID26
B6
IO
DIFFIO_TX96n
W5
UGRID27
B6
IO
DIFFIO_TX96p
W4
UGRID28
B6
IO
DIFFIO_RX96n
AB4
UGRID29
B8
IO
nRS
AF23
UGRID3
B6
IO
DIFFIO_RX96p
AB3
UGRID30
B6
IO
DIFFIO_TX95n
W7
UGRID31
B6
IO
DIFFIO_TX95p
W6
UGRID32
B6
IO
DIFFIO_RX95n
AB2
UGRID33
B6
IO
DIFFIO_RX95p
AB1
UGRID34
B6
IO
DIFFIO_TX94n
W9
UGRID35
B6
IO
DIFFIO_TX94p
W8
UGRID36
B6
IO
DIFFIO_RX94n
Y5
UGRID37
B6
IO
DIFFIO_RX94p
Y4
UGRID38
B6
IO
DIFFIO_TX93n
V5
UGRID39
B8
IO
RUnLU
AG17
UGRID4
B6
IO
DIFFIO_TX93p
V4
UGRID40
B6
IO
DIFFIO_RX93n
AA4
UGRID41
B6
IO
DIFFIO_RX93p
AA3
UGRID42
B6
IO
DIFFIO_TX92n
V7
UGRID43
B6
IO
DIFFIO_TX92p
V6
UGRID44
B6
IO
DIFFIO_RX92n
AA2
UGRID45
B6
IO
DIFFIO_RX92p
AA1
UGRID46
B6
IO
DIFFIO_TX91n
V10
UGRID47
B6
IO
DIFFIO_TX91p
V9
UGRID48
B6
IO
DIFFIO_RX91n
Y3
UGRID49
B8
IO
DEV_OE
AH17
UGRID5
B6
IO
DIFFIO_RX91p
Y2
UGRID50
B6
IO
DIFFIO_TX90n
U11
UGRID51
B6
IO
DIFFIO_TX90p
U10
UGRID52
Table 7-6. FPGA Pins Sorted by Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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